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| document no. u16603ej5v1ud00 (5th edition) date published march 2008 n printed in japan user?s manual v850es/sj2, v850es/sj2-h 32-bit single-chip microcontrollers hardware 2003, 2008 v850es/sj2: pd703264 pd703274 pd703284 pd70f3284 pd703264y pd703274y pd703284y pd70f3284y pd703265 pd703275 pd703285 pd70f3286 pd703265y pd703275y pd703285y pd70f3286y pd703266 pd703276 pd703286 pd70f3288 pd703266y pd703276y pd703286y pd70f3288y pd70f3264 pd70f3274 pd703287 pd70f3264y pd70f3274y pd703287y pd70f3266 pd70f3276 pd703288 pd70f3266y pd70f3276y pd703288y v850es/sj2-h: pd703265hy pd703275hy pd703285hy pd703287hy pd703266hy pd703276hy pd703286hy pd703288hy pd70f3266hy pd70f3276hy pd70f3286hy pd70f3288hy
user?s manual u16603ej5v1ud 2 [memo] user?s manual u16603ej5v1ud 3 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. power on/off sequence in the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. when switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. the correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. input of signal during power off state do not input signals or an i/o pull-up power supply while the device is not powered. the current injection that results from input of such a signal or i/o pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. notes for cmos devices 5 6 user?s manual u16603ej5v1ud 4 iecube is a registered trademark of nec corporation in japan and germany. minicube is a registered trademark of nec electronics corporation in jap an and germany or a trademark in the united states of america. eeprom, iebus, and inter equipment bus are trademarks of nec electronics corporation. windows and windows nt are either re gistered trademarks or trademarks of microsoft corporation in the united states and/or other countries. pc/at is a trademark of internati onal business machines corporation. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademar ks of sun microsystems, inc. user?s manual u16603ej5v1ud 5 these commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. diversion contrary to the law of that country is prohibited. the information in this document is current as of october, 2007. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec ele ctronics prod ucts is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) (1) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. (2) "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). ? ? ? ? ? ? m8e 02. 11-1 user?s manual u16603ej5v1ud 6 preface readers this manual is intended for users who wish to understand the functions of the v850es/sj2 and v850es/sj2-h products and design application systems using these products. purpose this manual is intended to give users an understanding of the har dware functions of the v850es/sj2 and v850es/sj2-h shown in the organization below. organization this manual is divided into two parts: hardware (this manual) and architecture ( v850es architecture user?s manual ). hardware architecture ? pin functions ? data types ? cpu function ? register set ? on-chip peripheral functions ? instruction format and instruction set ? flash memory programming ? interrupts and exceptions ? electrical specifications ? pipeline operation how to read this manual it is assumed that the readers of this m anual have general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. to understand the overall functions of the v850es/sj2 and v850es/sj2-h read this manual according to the contents . to find the details of a regi ster where the name is known use appendix c register index . register format the name of the bit whose number is in angle brackets (<>) in the figure of the register format of each register is defi ned as a reserved word in the device file. to understand the details of an instruction function refer to the v850es architecture user?s manual available separately. to know the electrical specificati ons of the v850es/sj2 and v850es/sj2-h see chapter 32 electrical specifications . the ?yyy bit of the xxx register? is described as the ?xxx.yyy bit? in this manual. note with caution that if ?xxx. yyy? is described as is in a program, however, the compiler/assembler cannot recognize it correctly. the mark user?s manual u16603ej5v1ud 7 conventions data significance: higher digits on the left and lower digits on the right active low representation: xxx (ove rscore over pin or signal name) memory map address: higher addresse s on the top and lower addresses on the bottom note: footnote for item marked with note in the text caution: information requiring particular attention remark: supplementary information numeric representation: binary ... xxxx or xxxxb decimal ... xxxx hexadecimal ... xxxxh prefix indicating power of 2 (address space, memory capacity): k (kilo): 2 10 = 1,024 m (mega): 2 20 = 1,024 2 g (giga): 2 30 = 1,024 3 user?s manual u16603ej5v1ud 8 related documents the related documents indicated in this pub lication may include preliminary versions. however, preliminary versions are not marked as such. documents related to v 850es/sj2, v850es/sj2-h document name document no. v850es architecture user?s manual u15943e v850es/sj2, v850es/sj2-h hardwa re user?s manual this manual documents related to development tools document name document no. ie-v850es-g1 (in-circuit emulator) u16313e ie-703288-g1-em1 (in-circuit em ulator option board) u16697e ie-v850e1-cd-nw (pcmcia card ty pe on-chip debug emulator) u16647e qb-v850essx2 (in-circuit emulator) u17091e qb-v850mini (on-chip debug emulator) u17638e qb-mini2 (on-chip debug emulator with programming function) u18371e operation u17293e c language u17291e assembly language u17292e ca850 ver. 3.00 c compiler package link directive u17294e pm+ ver. 6.30 project manager u18416e id850 ver. 3.00 integrated debugger operation u17358e id850qb ver. 3.40 integrated debugger operation u18604e tw850 ver. 2.00 performance analysis tuning tool u17241e operation u18601e sm+ system simulation user open interface u18212e basics u13430e installation u17419e technical u13431e rx850 ver. 3.20 real-time os task debugger u17420e basics u18165e installation u17421e technical u13772e rx850 pro ver. 3.21 real-time os task debugger u17422e az850 ver. 3.30 system performance analyzer u17423e pg-fp4 flash memory programmer u15260e pg-fp5 flash memory programmer u18865e user?s manual u16603ej5v1ud 9 contents chapter 1 introduction ...................................................................................................... ...........22 1.1 general ........................................................................................................................ .............22 1.2 features....................................................................................................................... .............26 1.3 application fields ............................................................................................................. ......27 1.4 ordering information ........................................................................................................... ...28 1.5 pin configuration (top view) ......................................... ........................................................30 1.6 function block configuration........................................ ........................................................33 1.6.1 internal bl ock di agram ......................................................................................................... ...... 33 1.6.2 internal units ................................................................................................................. ............. 34 chapter 2 pin funct ions.................................................................................................... ............37 2.1 list of pin functions.......................................................................................................... .....37 2.2 pin states ..................................................................................................................... ............49 2.3 pin i/o circuit types, i/o buffer power suppli es, and connection of unused pins........50 2.4 cautions ....................................................................................................................... ............54 chapter 3 cpu function..................................................................................................... ............55 3.1 features....................................................................................................................... .............55 3.2 cpu register set............................................................................................................... ......56 3.2.1 program regi ster set ........................................................................................................... ....... 57 3.2.2 system regi ster set............................................................................................................ ........ 58 3.3 operation modes ................................................................................................................ .....64 3.3.1 specifying oper ation mode ...................................................................................................... .. 64 3.4 address space .................................................................................................................. ......65 3.4.1 cpu address space.............................................................................................................. ..... 65 3.4.2 wraparound of cpu addr ess spac e .......................................................................................... 66 3.4.3 memory map..................................................................................................................... ......... 67 3.4.4 areas .......................................................................................................................... ............... 69 3.4.5 recommended use of address s pace ....................................................................................... 75 3.4.6 peripheral i/o regist ers....................................................................................................... ....... 77 3.4.7 programmable peripheral i/o regist ers...................................................................................... 90 3.4.8 special r egister s .............................................................................................................. .......... 90 3.4.9 cauti ons ....................................................................................................................... ............. 94 chapter 4 port f unctions................................................................................................... .........99 4.1 features....................................................................................................................... .............99 4.2 basic port configuration ....................................................................................................... .99 4.3 port configuration........................................................... .................................................. ....100 4.3.1 port 0......................................................................................................................... .............. 104 4.3.2 port 1......................................................................................................................... .............. 107 4.3.3 port 3......................................................................................................................... .............. 108 4.3.4 port 4......................................................................................................................... .............. 114 4.3.5 port 5......................................................................................................................... .............. 117 user?s manual u16603ej5v1ud 10 4.3.6 port 6 ......................................................................................................................... ..............121 4.3.7 port 7 ......................................................................................................................... ..............125 4.3.8 port 8 ......................................................................................................................... ..............127 4.3.9 port 9 ......................................................................................................................... ..............129 4.3.10 port cd ........................................................................................................................ ............137 4.3.11 port cm ........................................................................................................................ ...........138 4.3.12 port cs ........................................................................................................................ ............140 4.3.13 port ct ........................................................................................................................ ............142 4.3.14 port dh ........................................................................................................................ ............144 4.3.15 port dl ........................................................................................................................ ............146 4.4 block diagrams................................................................................................................. .... 148 4.5 port register settings when alternate function is used ................................................ 185 4.6 cautions ....................................................................................................................... ......... 195 4.6.1 cautions on se tting port pins .................................................................................................. .195 4.6.2 cautions on bit manipulation instru ction for port n r egister (pn) ...............................................198 4.6.3 cautions on on-ch ip debug pi ns...............................................................................................19 9 4.6.4 cautions on p05/in tp2/drst pin...........................................................................................199 4.6.5 cautions on p10, p11, and p53 pi ns when power is turned on ............................................... 199 4.6.6 hysteresis char acterist ics ..................................................................................................... ...199 4.6.7 cautions on separ ate bus mode ..............................................................................................199 chapter 5 bus control function ................................ .......................................................... 20 0 5.1 features....................................................................................................................... .......... 200 5.2 bus control pins............................................................................................................... .... 201 5.2.1 pin status when internal rom, internal ra m, or on-chip peripher al i/o is a ccessed...............201 5.2.2 pin status in eac h operation mode ...........................................................................................201 5.3 memory block function....................................................................................................... 202 5.4 external bus interface mode control function ......... ........................................................ 203 5.5 bus access ..................................................................................................................... ...... 204 5.5.1 number of clo cks for a ccess.................................................................................................... 204 5.5.2 bus size setti ng func tion ...................................................................................................... ....205 5.5.3 access by bus si ze ............................................................................................................. .....206 5.6 wait function .................................................................................................................. ...... 213 5.6.1 programmable wait function ....................................................................................................2 13 5.6.2 external wait func tion......................................................................................................... ......214 5.6.3 relationship between programmabl e wait and exte rnal wa it ................................................... 215 5.6.4 programmable address wait func tion .......................................................................................216 5.7 idle state insertion function ............................................................................................... 217 5.8 bus hold function.............................................................................................................. .. 218 5.8.1 functional outlin e............................................................................................................. ........218 5.8.2 bus hold pr ocedur e............................................................................................................. .....219 5.8.3 operation in power save mode ................................................................................................219 5.9 bus priority ................................................................................................................... ........ 220 5.10 bus timing ..................................................................................................................... ....... 221 chapter 6 clock generation function .................... .......................................................... 227 6.1 overview....................................................................................................................... ......... 227 user?s manual u16603ej5v1ud 11 6.2 configuration .................................................................................................................. .......228 6.3 registers ...................................................................................................................... ..........230 6.4 operation...................................................................................................................... ..........235 6.4.1 operation of each cl ock........................................................................................................ ... 235 6.4.2 clock output functi on .......................................................................................................... ..... 235 6.5 pll function................................................................................................................... .......236 6.5.1 overvi ew ....................................................................................................................... .......... 236 6.5.2 regist ers ...................................................................................................................... ........... 236 6.5.3 usage .......................................................................................................................... ............ 239 chapter 7 16-bit timer/event counter p (tmp) .. ...............................................................240 7.1 overview....................................................................................................................... ..........240 7.2 functions ...................................................................................................................... .........240 7.3 configuration .................................................................................................................. .......241 7.4 registers ...................................................................................................................... ..........243 7.5 timer output operations............................................ ..........................................................25 6 7.6 operation...................................................................................................................... ..........257 7.6.1 interval timer mode (tpnmd2 to tpnmd0 bi ts = 000)............................................................. 264 7.6.2 external event count mode (tpn md2 to tpnmd0 bits = 001)................................................. 276 7.6.3 external trigger pulse output mode (tpnmd2 to tpnmd0 bits = 010) ..................................... 285 7.6.4 one-shot pulse output mode (tpn md2 to tpnmd0 bits = 011) .............................................. 297 7.6.5 pwm output mode (tpnmd2 to tpnmd0 bi ts = 100).............................................................. 304 7.6.6 free-running timer mode (tpnmd2 to tpnmd0 bi ts = 101) .................................................... 313 7.6.7 pulse width measurement mode (tpn md2 to tpnmd0 bits = 110) ........................................ 331 7.7 selector function .............................................................................................................. ....337 chapter 8 16-bit timer/event counter q (tmq) ... .............................................................339 8.1 overview....................................................................................................................... ..........339 8.2 functions ...................................................................................................................... .........339 8.3 configuration .................................................................................................................. .......340 8.4 registers ...................................................................................................................... ..........342 8.5 timer output operations .......................................................................................................3 58 8.6 operation...................................................................................................................... ..........359 8.6.1 interval timer mode (tq0md2 to tq0md0 bi ts = 000) ............................................................ 366 8.6.2 external event count mode (tq0 md2 to tq0md0 bits = 001) ................................................ 377 8.6.3 external trigger pulse output mode (tq0md2 to tq0md0 bits = 010) .................................... 387 8.6.4 one-shot pulse output mode (tq0 md2 to tq0md0 bits = 011) ............................................. 400 8.6.5 pwm output mode (tq0md2 to tq0md0 bi ts = 100) ............................................................. 409 8.6.6 free-running timer mode (tq0md2 to tq0md0 bi ts = 101) ................................................... 420 8.6.7 pulse width measurement mode (tq0 md2 to tq0md0 bits = 110)........................................ 441 8.7 selector function .............................................................................................................. ....446 chapter 9 16-bit interval timer m (tmm).......... ...................................................................447 9.1 overview....................................................................................................................... ..........447 9.2 configuration .................................................................................................................. .......448 9.3 register ....................................................................................................................... ...........449 user?s manual u16603ej5v1ud 12 9.4 operation...................................................................................................................... ......... 450 9.4.1 interval ti mer m ode ............................................................................................................ ......450 9.4.2 cauti ons....................................................................................................................... ............454 chapter 10 watch timer functions ............................ .......................................................... 455 10.1 functions...................................................................................................................... ......... 455 10.2 configuration .................................................................................................................. ...... 456 10.3 control registers .............................................................................................................. ... 458 10.4 operation...................................................................................................................... ......... 462 10.4.1 operation as watch ti mer ....................................................................................................... ..462 10.4.2 operation as in terval timer.................................................................................................... ...463 10.4.3 cauti ons....................................................................................................................... ............464 chapter 11 functions of watchdog timer 2 .. ................................................................. 465 11.1 functions...................................................................................................................... ......... 465 11.2 configuration .................................................................................................................. ...... 466 11.3 registers ...................................................................................................................... ......... 467 11.4 operation...................................................................................................................... ......... 469 chapter 12 real-time output function (rto).. ................................................................. 470 12.1 function....................................................................................................................... .......... 470 12.2 configuration .................................................................................................................. ...... 471 12.3 registers ...................................................................................................................... ......... 473 12.4 operation...................................................................................................................... ......... 475 12.5 usage .......................................................................................................................... ........... 476 12.6 cautions ....................................................................................................................... ......... 476 chapter 13 a/d converter ................................................................................................... ...... 477 13.1 overview....................................................................................................................... ......... 477 13.2 functions...................................................................................................................... ......... 477 13.3 configuration .................................................................................................................. ...... 478 13.4 registers ...................................................................................................................... ......... 481 13.5 operation...................................................................................................................... ......... 492 13.5.1 basic oper ation ................................................................................................................ ........492 13.5.2 conversion operat ion ti ming .................................................................................................... 493 13.5.3 trigger mode ................................................................................................................... ........494 13.5.4 operati on m ode ................................................................................................................. ......496 13.5.5 power-fail co mpare mode ........................................................................................................ 500 13.6 cautions ....................................................................................................................... ......... 505 13.7 how to read a/d converter characteristics table... ........................................................ 510 chapter 14 d/a converter ................................................................................................... ...... 514 14.1 functions...................................................................................................................... ......... 514 14.2 configuration .................................................................................................................. ...... 515 14.3 registers ...................................................................................................................... ......... 516 user?s manual u16603ej5v1ud 13 14.4 operation...................................................................................................................... ..........517 14.4.1 operation in normal mode ....................................................................................................... 517 14.4.2 operation in real-t ime output mode ......................................................................................... 517 14.4.3 cauti ons ....................................................................................................................... ........... 518 chapter 15 asynchronous serial interface a (uarta) ..............................................519 15.1 mode switching of uarta and other serial interf aces....................................................519 15.1.1 csib4 and uarta0 m ode switch ing ...................................................................................... 519 15.1.2 uarta2 and i 2 c00 mode swit ching ........................................................................................ 520 15.1.3 uarta1 and i 2 c02 mode swit ching ........................................................................................ 521 15.2 features....................................................................................................................... ...........522 15.3 configuration .................................................................................................................. .......523 15.4 registers ...................................................................................................................... ..........525 15.5 interrupt request signals......................... ............................................................................5 32 15.6 operation...................................................................................................................... ..........533 15.6.1 data fo rmat.................................................................................................................... .......... 533 15.6.2 sbf transmission/rec eption fo rmat.......................................................................................... 535 15.6.3 sbf trans missi on ............................................................................................................... ..... 537 15.6.4 sbf rec eptio n.................................................................................................................. ........ 538 15.6.5 uart trans missi on.............................................................................................................. .... 540 15.6.6 continuous transmi ssion proc edure ........................................................................................ 541 15.6.7 uart rec eptio n ................................................................................................................. ...... 543 15.6.8 reception errors ............................................................................................................... ....... 544 15.6.9 parity types and operat ions .................................................................................................... . 546 15.6.10 receive data noi se f ilter ...................................................................................................... .... 547 15.7 dedicated baud rate generator ................................. .........................................................548 15.8 cautions ....................................................................................................................... ..........556 chapter 16 3-wire variable-length serial i/o (csib) ....................................................557 16.1 mode switching of csib and other serial interfaces ........................................................557 16.1.1 csib4 and uarta0 m ode switch ing ...................................................................................... 557 16.1.2 csib0 and i 2 c01 mode swit ching ............................................................................................ 558 16.2 features....................................................................................................................... ...........559 16.3 configuration .................................................................................................................. .......560 16.4 registers ...................................................................................................................... ..........562 16.5 interrupt request signals......................... ............................................................................5 70 16.6 operation...................................................................................................................... ..........571 16.6.1 single transfer mode (master mode, transmi ssion m ode) ....................................................... 571 16.6.2 single transfer mode (master mode, recept ion m ode)............................................................. 573 16.6.3 single transfer mode (master mode, transmission/rec eption m ode)........................................ 575 16.6.4 single transfer mode (slave mode, transmi ssion m ode) .......................................................... 577 16.6.5 single transfer mode (slave mode, recept ion m ode) ............................................................... 579 16.6.6 single transfer mode (slave mode, transmission/rec eption m ode) .......................................... 581 16.6.7 continuous transfer mode (master mode, transmi ssion m ode) ............................................... 583 16.6.8 continuous transfer mode (master mode, recept ion m ode)..................................................... 585 16.6.9 continuous transfer mode (master m ode, transmission/re ception mode) ................................ 588 16.6.10 continuous transfer mode (slave mode, transmi ssion m ode).................................................. 592 user?s manual u16603ej5v1ud 14 16.6.11 continuous transfer mode (slave mode, recept ion m ode) ....................................................... 594 16.6.12 continuous transfer mode (slave m ode, transmission/re ception mode) ..................................597 16.6.13 reception error ................................................................................................................ ........601 16.6.14 clock ti ming ................................................................................................................... ..........602 16.7 output pins .................................................................................................................... ....... 604 16.8 baud rate generator............................................................................................................ 605 16.8.1 baud rate generatio n ........................................................................................................... ....606 16.9 cautions ....................................................................................................................... ......... 607 chapter 17 i 2 c bus ......................................................................................................................... . 608 17.1 mode switching of i 2 c bus and other serial interfaces ..... .............................................. 608 17.1.1 uarta2 and i 2 c00 mode swit ching .........................................................................................608 17.1.2 csib0 and i 2 c01 mode swit ching ............................................................................................609 17.1.3 uarta1 and i 2 c02 mode swit ching .........................................................................................610 17.2 features....................................................................................................................... .......... 611 17.3 configuration .................................................................................................................. ...... 612 17.4 registers ...................................................................................................................... ......... 616 17.5 i 2 c bus mode functions....................................................................................................... 632 17.5.1 pin confi guratio n .............................................................................................................. ........632 17.6 i 2 c bus definitions and control methods ..................... ..................................................... 633 17.6.1 start c onditi on................................................................................................................ ..........633 17.6.2 addre sses...................................................................................................................... ..........634 17.6.3 transfer direction specific ation ............................................................................................... .635 17.6.4 ack ............................................................................................................................ .............636 17.6.5 stop condi tion ................................................................................................................. .........637 17.6.6 wait state..................................................................................................................... ............638 17.6.7 wait state cance llation me thod ................................................................................................6 40 17.7 i 2 c interrupt request signals (intiicn) ......................... ..................................................... 641 17.7.1 master devic e operat ion........................................................................................................ ...642 17.7.2 slave device operation (when receiving slave address (addr ess matc h))................................645 17.7.3 slave device operation (when re ceiving extens ion c ode) ........................................................ 649 17.7.4 operation without communica tion ............................................................................................653 17.7.5 arbitration loss operation (operation as slave after arbi tration loss) .........................................654 17.7.6 operation when arbitration loss occurs ( no communication after arbitrati on loss) ...................656 17.8 interrupt request signal (intiicn) generation ti ming and wait control....................... 663 17.9 address match detection method ... ................................................................................... 664 17.10 error detection................................................................................................................ ...... 664 17.11 extension code................................................................................................................. .... 665 17.12 arbitration .................................................................................................................... ......... 666 17.13 wakeup function................................................................................................................ .. 667 17.14 communication reservation............................................................................................... 668 17.14.1 when communication reservation function is enabled (iicfn.iicr svn bit = 0) .......................668 17.14.2 when communication reservation function is disabled (iicfn.ii crsvn bit = 1).......................672 17.15 cautions ....................................................................................................................... ......... 673 17.16 communication operations ................................................................................................ 674 17.16.1 master operation in si ngle master system ................................................................................675 17.16.2 master operation in multimaste r system ..................................................................................676 17.16.3 slave oper ation................................................................................................................ ........679 user?s manual u16603ej5v1ud 15 17.17 timing of data communication ...........................................................................................683 chapter 18 iebus controller..................................... ........................................................... ....690 18.1 functions ...................................................................................................................... .........690 18.1.1 communication protoc ol of i ebus ........................................................................................... 690 18.1.2 determination of bus mast ership (arb itrati on).......................................................................... 691 18.1.3 communicati on m ode............................................................................................................. . 691 18.1.4 communicati on addres s .......................................................................................................... 691 18.1.5 broadcast comm unicati on ....................................................................................................... 6 92 18.1.6 transfer format of iebus ....................................................................................................... .. 692 18.1.7 transfer data .................................................................................................................. ......... 702 18.1.8 bit fo rmat ..................................................................................................................... ............ 704 18.2 configuration .................................................................................................................. .......705 18.3 registers ...................................................................................................................... ..........707 18.4 interrupt operations of iebus cont roller............................................................................736 18.4.1 interrupt cont rol bl ock ........................................................................................................ ...... 736 18.4.2 example of ident ifying in terrupt ............................................................................................... 739 18.4.3 interrupt s ource list .......................................................................................................... ........ 742 18.4.4 communication error sour ce processi ng list ............................................................................ 743 18.5 interrupt request signal generation timing and main cpu processing........................745 18.5.1 master tr ansmissi on ............................................................................................................ .... 745 18.5.2 master re ceptio n............................................................................................................... ....... 747 18.5.3 slave trans missi on ............................................................................................................. ..... 749 18.5.4 slave rec eptio n................................................................................................................ ........ 751 18.5.5 interval of occurrence of interrupt request signal for iebus cont rol ......................................... 753 chapter 19 can controller ......................................... ......................................................... ....757 19.1 overview....................................................................................................................... ..........757 19.1.1 featur es ....................................................................................................................... ........... 757 19.1.2 overview of func tions .......................................................................................................... .... 758 19.1.3 configur ation .................................................................................................................. ......... 759 19.2 can protocol ................................................................................................................... ......760 19.2.1 frame fo rmat ................................................................................................................... ........ 760 19.2.2 frame types .................................................................................................................... ........ 761 19.2.3 data frame and re mote frame.................................................................................................. 76 1 19.2.4 error fr ame .................................................................................................................... .......... 768 19.2.5 overload frame................................................................................................................. ....... 769 19.3 functions ...................................................................................................................... .........770 19.3.1 determining bus prio rity....................................................................................................... .... 770 19.3.2 bit stu ffing................................................................................................................... ............. 770 19.3.3 multi ma sters .................................................................................................................. ......... 770 19.3.4 multi cast ..................................................................................................................... ............ 770 19.3.5 can sleep mode/can st op mode func tion .............................................................................. 771 19.3.6 error contro l func tion ......................................................................................................... ...... 771 19.3.7 baud rate cont rol func tion..................................................................................................... ... 778 19.4 connection with target system ................................. .........................................................782 19.5 internal registers of can controller ..................................................................................783 user?s manual u16603ej5v1ud 16 19.5.1 can controller c onfigurat ion ................................................................................................... .783 19.5.2 register a ccess ty pe ........................................................................................................... ....784 19.5.3 register bit c onfigurat ion ..................................................................................................... ....818 19.6 registers ...................................................................................................................... ......... 822 19.7 bit set/clear function ......................................................................................................... . 857 19.8 can controller initializat ion................................................................................................ 85 9 19.8.1 initialization of can m odule................................................................................................... ..859 19.8.2 initialization of message buffer ............................................................................................... .859 19.8.3 redefinition of message bu ffer ................................................................................................8 59 19.8.4 transition from initializati on mode to operat ion m ode.............................................................. 861 19.8.5 resetting error counter cn erc of can module ......................................................................861 19.9 message reception .............................................................................................................. 862 19.9.1 message rec eptio n .............................................................................................................. ....862 19.9.2 reading recept ion dat a......................................................................................................... ...863 19.9.3 receive history list func tion .................................................................................................. ...864 19.9.4 mask func tion.................................................................................................................. .........866 19.9.5 multi buffer receiv e block f uncti on............................................................................................ 868 19.9.6 remote frame recept ion ......................................................................................................... .869 19.10 message transmission ........................................................................................................ 870 19.10.1 message trans missi on ........................................................................................................... ..870 19.10.2 transmit history list func tion ................................................................................................. ...872 19.10.3 automatic block tr ansmission ( abt) ........................................................................................874 19.10.4 transmission abor t proc ess..................................................................................................... 875 19.10.5 remote frame transmissi on .....................................................................................................8 76 19.11 power saving modes............................................................................................................ 8 77 19.11.1 can sleep mode................................................................................................................. .....877 19.11.2 can stop mode .................................................................................................................. .....879 19.11.3 example of using pow er saving modes ....................................................................................880 19.12 interrupt function............................................................................................................. .... 881 19.13 diagnosis functions and special operational mode s ..................................................... 882 19.13.1 receive-onl y m ode .............................................................................................................. ....882 19.13.2 single-shot mode............................................................................................................... ......883 19.13.3 self-tes t mode................................................................................................................. .........884 19.13.4 transmission/reception operati on in each operat ion m ode...................................................... 885 19.14 time stamp function ........................................................................................................... 8 86 19.14.1 time stamp functi on ............................................................................................................ ....886 19.15 baud rate settings............................................................................................................. .. 888 19.15.1 bit rate setti ng condi tions.................................................................................................... .....888 19.15.2 representative examples of baud rate settings .......................................................................892 19.16 operation of can contro ller ............................................................................................... 896 chapter 20 dma function (dma controller) ..... .............................................................. 922 20.1 features....................................................................................................................... .......... 922 20.2 configuration .................................................................................................................. ...... 923 20.3 registers ...................................................................................................................... ......... 924 20.4 transfer targets ............................................................................................................... .... 933 20.5 transfer modes ................................................................................................................. .... 933 20.6 transfer types ................................................................................................................. ..... 934 user?s manual u16603ej5v1ud 17 20.7 dma channel priorities ........................................................................................................9 35 20.8 time related to dma transfer.............................................................................................935 20.9 dma transfer start factors ............. ....................................................................................936 20.10 dma abort factors.............................................................................................................. ..937 20.11 end of dma transfer............................................................................................................ .937 20.12 operation timing............................................................................................................... ....937 20.13 cautions ....................................................................................................................... ..........942 chapter 21 crc functio n .................................................................................................... ........946 21.1 functions ...................................................................................................................... .........946 21.2 configuration .................................................................................................................. .......946 21.3 registers ...................................................................................................................... ..........947 21.4 operation...................................................................................................................... ..........948 21.5 usage.......................................................................................................................... ............949 chapter 22 interrupt/exception processing fu nction ...............................................951 22.1 features....................................................................................................................... ...........951 22.2 non-maskable interrupts .......................... ............................................................................95 6 22.2.1 operat ion...................................................................................................................... ........... 958 22.2.2 restore........................................................................................................................ ............ 959 22.2.3 np fl ag........................................................................................................................ ............. 960 22.3 maskable interrupts ............................................................................................................ ..961 22.3.1 operat ion...................................................................................................................... ........... 961 22.3.2 restore........................................................................................................................ ............ 963 22.3.3 priorities of ma skable inte rrupts .............................................................................................. 964 22.3.4 interrupt control r egister ( xxicn) ............................................................................................. . 968 22.3.5 interrupt mask registers 0 to 4 (imr0 to imr4 )........................................................................ 972 22.3.6 in-service priority register (ispr)............................................................................................ . 974 22.3.7 id flag ........................................................................................................................ .............. 975 22.3.8 watchdog timer mode regi ster 2 (w dtm2) ............................................................................. 975 22.4 software exception ............................................................................................................. ..976 22.4.1 operat ion...................................................................................................................... ........... 976 22.4.2 restore........................................................................................................................ ............ 977 22.4.3 ep fl ag........................................................................................................................ ............. 978 22.5 exception trap ................................................................................................................. .....979 22.5.1 illegal opcode definit ion ...................................................................................................... ..... 979 22.5.2 debug tr ap..................................................................................................................... .......... 981 22.6 external interrupt request input pins (nmi and intp0 to intp8) ....................................983 22.6.1 noise elim inatio n .............................................................................................................. ....... 983 22.6.2 edge detec tion................................................................................................................. ........ 983 22.7 interrupt acknowledge time of cpu ...................................................................................989 22.8 periods in which interrupts are not acknowledged by cpu...........................................992 22.9 cautions ....................................................................................................................... ..........992 chapter 23 key interrupt function ......................... .............................................................993 23.1 function ....................................................................................................................... ..........993 user?s manual u16603ej5v1ud 18 23.2 register ....................................................................................................................... .......... 994 23.3 cautions ....................................................................................................................... ......... 994 chapter 24 standby function ................................................................................................ .. 995 24.1 overview....................................................................................................................... ......... 995 24.2 registers ...................................................................................................................... ......... 997 24.3 halt mode...................................................................................................................... .... 1000 24.3.1 setting and operati on stat us ..................................................................................................1 000 24.3.2 releasing ha lt m ode...........................................................................................................1 000 24.4 idle1 mode ..................................................................................................................... .... 1002 24.4.1 setting and operati on stat us ..................................................................................................1 002 24.4.2 releasing id le1 m ode ..........................................................................................................1 003 24.5 idle2 mode ..................................................................................................................... .... 1005 24.5.1 setting and operati on stat us ..................................................................................................1 005 24.5.2 releasing id le2 m ode ..........................................................................................................1 005 24.5.3 securing setup time when releasing id le2 m ode ................................................................. 1007 24.6 stop mode...................................................................................................................... .... 1008 24.6.1 setting and operati on stat us ..................................................................................................1 008 24.6.2 releasing st op m ode .......................................................................................................... 10 08 24.6.3 securing oscillation stabilization ti me when releasi ng stop mode .......................................1011 24.7 subclock operation mode ................................................................................................. 1012 24.7.1 setting and operati on stat us ..................................................................................................1 012 24.7.2 releasing subclock operation mode ......................................................................................1012 24.8 sub-idle mode .................................................................................................................. . 1014 24.8.1 setting and operati on stat us ..................................................................................................1 014 24.8.2 releasing sub- idle m ode ..................................................................................................... 101 5 chapter 25 reset functions ................................................................................................. .. 1017 25.1 overview....................................................................................................................... ....... 1017 25.2 registers to check reset source.................................. ................................................... 1019 25.3 operation...................................................................................................................... ....... 1020 25.3.1 reset operation vi a reset pin .............................................................................................1020 25.3.2 reset operation by watc hdog timer 2 (w dt2res) ................................................................1022 25.3.3 reset operation by low-voltage detec tor (lvires) (v 850es/sj2 only) .................................1024 25.3.4 reset operation by clo ck monitor (c lmres) ........................................................................1025 25.3.5 operation after re set rel ease .................................................................................................1 027 25.3.6 reset function oper ation fl ow.................................................................................................1 029 25.4 valid/invalid of internal ram data ............................ ........................................................ 1030 chapter 26 clock monitor ................................................................................................... ... 1031 26.1 functions...................................................................................................................... ....... 1031 26.2 configuration .................................................................................................................. .... 1031 26.3 register ....................................................................................................................... ........ 1032 26.4 operation...................................................................................................................... ....... 1033 chapter 27 low-voltage detector ............................. ........................................................ 1036 user?s manual u16603ej5v1ud 19 27.1 functions ...................................................................................................................... .......1036 27.2 configuration .................................................................................................................. .....1036 27.3 registers ...................................................................................................................... ........1037 27.4 operation...................................................................................................................... ........1039 27.4.1 to use for internal re set signal (l vires) .............................................................................. 1039 27.4.2 to use for inte rrupt (intlvi).................................................................................................. 1040 27.5 ram retention voltage detection operat ion (provided to both v850es/sj2 and v850es/sj2-h) .................................................................................................................. ...1041 27.6 emulation function (provided to both v850es/s j2 and v850es/sj2-h) .....................1042 chapter 28 regulator ........................................................................................................ ........1043 28.1 outline ........................................................................................................................ ..........1043 28.2 operation...................................................................................................................... ........1044 chapter 29 rom correction function .................... ...........................................................1045 29.1 overview....................................................................................................................... ........1045 29.2 registers ...................................................................................................................... ........1046 29.3 rom correction operation and program flow ......... .......................................................1047 29.4 cautions ....................................................................................................................... ........1049 chapter 30 flash memory.................................................................................................... .....1050 30.1 features....................................................................................................................... .........1050 30.2 memory configuration ................................. .......................................................................105 1 30.3 functional outline............................................................................................................. ..1054 30.4 rewriting by dedicated flash memory programmer .......................................................1057 30.4.1 programming env ironment .................................................................................................... 1057 30.4.2 communicati on mode ............................................................................................................ 1 058 30.4.3 flash memory cont rol ........................................................................................................... . 1065 30.4.4 selection of comm unication mode ......................................................................................... 1066 30.4.5 communication commands ................................................................................................... 1067 30.4.6 pin connec tion ................................................................................................................. ...... 1068 30.5 rewriting by self programming............... ..........................................................................1072 30.5.1 overvi ew ....................................................................................................................... ........ 1072 30.5.2 featur es ....................................................................................................................... ......... 1073 30.5.3 standard self progr amming fl ow ............................................................................................ 1074 30.5.4 flash f uncti ons ................................................................................................................ ...... 1075 30.5.5 pin proc essi ng ................................................................................................................. ...... 1075 30.5.6 internal res ources used ........................................................................................................ . 1076 chapter 31 on-chip debug function....................... .............................................................1077 31.1 features....................................................................................................................... .........1077 31.2 connection circuit example ....................................... .......................................................1078 31.3 interface signals.............................................................................................................. ....1078 31.4 register ....................................................................................................................... .........1080 31.5 operation...................................................................................................................... ........1082 31.6 rom security function.......................................................................................................108 3 user?s manual u16603ej5v1ud 20 31.6.1 security id .................................................................................................................... .........1083 31.6.2 setti ng ........................................................................................................................ ...........1084 31.7 cautions ....................................................................................................................... ....... 1086 chapter 32 electrical specifications ....................... ........................................................ 1087 32.1 absolute maximum ratings .............................................................................................. 1087 32.2 capacitance.................................................................................................................... ..... 1089 32.3 operating conditions......................................................................................................... 10 89 32.4 oscillator characteristi cs .................................................................................................. 109 0 32.4.1 main clock oscillator characteri stics .......................................................................................109 0 32.4.2 subclock oscillator c haracterist ics .........................................................................................109 3 32.4.3 pll characte ristics ............................................................................................................ ....1094 32.4.4 internal oscillator characteri stics............................................................................................ 1094 32.5 regulator characteristi cs.................................................................................................. 1095 32.6 dc characteristics ............................................................................................................. 1096 32.6.1 i/o level ...................................................................................................................... ...........1096 32.6.2 supply cu rrent................................................................................................................. .......1098 32.7 data retention characteristics . ........................................................................................ 1100 32.8 ac characteristics ............................................................................................................. 1101 32.8.1 clkout output timi ng........................................................................................................... 1102 32.8.2 bus ti ming ..................................................................................................................... .........1102 32.9 basic operation ................................................................................................................ .. 1116 32.10 flash memory programming characteristics............ ...................................................... 1125 chapter 33 package drawing ................................................................................................ 1 128 chapter 34 recommended soldering conditions. ........................................................ 1129 appendix a development tools............................................................................................. 11 30 a.1 software package ............................................................................................................... 1135 a.2 language processing software ........................................................................................ 1135 a.3 control software............................................................................................................... .. 1135 a.4 debugging tools (hardware) .......................................... .................................................. 1136 a.4.1 when using in-circuit em ulator ie-v 850es-g1 ...................................................................... 1136 a.4.2 when using iecu be qb-v850 essx2 .................................................................................. 1138 a.4.3 when using on-chip debug emul ator ie-v850e 1-cd-nw ......................................................1140 a.4.4 when using minicu be qb-v850m ini ..................................................................................1141 a.5 debugging tools (software).............................................................................................. 1142 a.6 embedded software ........................................................................................................... 114 3 a.7 flash memory writing tools ............................................................................................. 1143 appendix b major differences between v850es/sj2 and v850es/sj2-h............... 1144 appendix c register index .................................................................................................. ..... 1146 user?s manual u16603ej5v1ud 21 appendix d instruction set list........................................................................................... .1162 d.1 conventions.................................................................................................................... .....1162 d.2 instruction set (in alphabetical order) .................. ...........................................................1165 appendix e revision history ................................................................................................ ....1172 e.1 major revisions in this edition ................................. ........................................................1172 e.2 revision history of previous editions ................... ...........................................................1182 user?s manual u16603ej5v1ud 22 chapter 1 introduction the v850es/sj2 and v850es/sj2-h are products in t he nec electronics v850 single-chip microcontrollers designed for low-power operation for real-time control applications. 1.1 general the v850es/sj2 and v850es/sj2-h are 32-bit single-chip microcontrollers that include the v850es cpu core and peripheral functions such as rom/ram, a timer/counter, se rial interfaces, an a/d converter, and a d/a converter. some models of the v850es/sj2 and v 850es/sj2-h are provided with iebus tm (inter equipment bus tm ) or can (controller area network) as an automotive lan. in addition to high real-time response characteristics and 1-clock-pitch basic instructions, the v850es/sj2 and v850es/sj2-h feature multiply instruct ions, saturated operation instructions , bit manipulation instructions, etc., realized by a hardware multiplier, as optimum instructions for digital servo control applications. moreover, as a real- time control system, the v850es/sj2 an d v850es/sj2-h enable an extremely high cost-performance for applications that require a low power consumption, such as audio and car audio. table 1-1 lists the products of the v850es/sj2 and v850es/sj2-h. models of the v850es/sj2 and v850es/ sj2-h with simplified i/o, timer/counter, and serial interface functions, v850es/sg2 and v850es/sg2-h, are also available. see table 1-2 v850es/sg2, v850es/sg2-h product list . chapter 1 introduction user?s manual u16603ej5v1ud 23 table 1-1. v850es/sj2, v850es/sj2-h product list rom maskable interrupts function part number type size ram size operating frequency (max.) i 2 c iebus can external internal non-maskable interrupts pd703264 none pd703264y mask rom on-chip pd70f3264 none pd70f3264y flash memory 384 kb 32 kb on-chip pd703265 none pd703265y 20 mhz 60 pd703265hy 512 kb 40 kb 32 mhz on-chip 59 pd703266 none pd703266y 20 mhz 60 pd703266hy mask rom 32 mhz on-chip 59 pd70f3266 none pd70f3266y 20 mhz 60 pd70f3266hy flash memory 640 kb 48 kb 32 mhz on-chip none 59 pd703274 none pd703274y mask rom on-chip pd70f3274 none pd70f3274y flash memory 384 kb 32 kb on-chip pd703275 none pd703275y 20 mhz 64 pd703275hy 512 kb 40 kb 32 mhz on-chip 63 pd703276 none pd703276y 20 mhz 64 pd703276hy mask rom 32 mhz on-chip 63 pd70f3276 none pd70f3276y 20 mhz 64 pd70f3276hy flash memory 640 kb 48 kb 32 mhz on-chip on-chip none 63 pd703284 none pd703284y mask rom on-chip pd70f3284 none pd70f3284y flash memory 384 kb 32 kb on-chip pd703285 none pd703285y 20 mhz 64 pd703285hy 512 kb 40 kb 32 mhz on-chip 63 pd703286 none pd703286y 20 mhz 64 pd703286hy mask rom 32 mhz on-chip 63 pd70f3286 none pd70f3286y 20 mhz 64 pd70f3286hy flash memory 640 kb 48 kb 32 mhz on-chip 1 ch 63 pd703287 none pd703287y 20 mhz 68 pd703287hy 512 kb 40 kb 32 mhz on-chip 67 pd703288 none pd703288y 20 mhz 68 pd703288hy mask rom 32 mhz on-chip 67 pd70f3288 none pd70f3288y 20 mhz 68 pd70f3288hy flash memory 640 kb 48 kb 32 mhz on-chip none 2 ch 9 67 2 remark the part numbers of the v850es/sj2 and v850es/sj 2-h are shown as follows in this manual. chapter 1 introduction user?s manual u16603ej5v1ud 24 ? v850es/sj2 pd703264, 703264y, 703265, 703265y, 703266, 703266y, 703274, 703274y, 703275, 703275y, 703276, 703276y, 703284, 703284y, 703285, 703285y, 703286, 703286y, 703287, 703287y, 703288, 703288y, 70f3264, 70f3264y, 70f3266, 70f3266 y, 70f3274, 70f3274y, 70f3276, 70f3276y, 70f3284, 70f3284y, 70f3286, 70f3286y, 70f3288, 70f3288y ? v850es/sj2-h pd703265hy, 703266hy, 70f3266hy, 703275hy, 703276hy, 70f3276hy, 703285hy, 703286hy, 703287hy, 703288hy, 70f3286hy, 70f3288hy ? mask rom versions pd703264, 703264y, 703265, 703265y, 703265hy, 703266, 703266y, 703266hy, 703274, 703274y, 703275, 703275y, 703275hy, 703276, 703276y, 703276hy, 703284, 703284y, 703285, 703285y, 703285hy, 703286, 703286y, 703286hy, 703287, 703287y, 703287hy, 703288, 703288y, 703288hy ? flash memory versions pd70f3264, 70f3264y, 70f3266, 70f3266y, 70f3266hy, 70f3274, 70f3274y, 70f3276, 70f3276y, 70f3276hy, 70f3284, 70f3284y, 70f3286, 70f3286y, 70f3286hy, 70f3288, 70f3288y, 70f3288hy ? i 2 c bus versions (y products): all v850es/sj2-h products have an on-chip i 2 c bus. pd703264y, 703265y, 703265hy, 703266y, 703266hy, 703274y, 703275y, 703275hy, 703276y, 703276hy, 703284y, 703285y, 703285hy, 703286y, 703286hy, 703287y, 703287hy, 703288y, 703288hy, 70f3264y, 70f3266y, 70f3266hy, 70f3274y, 70f3276y, 70f3276 hy, 70f3284y, 70f3286y, 70f3286hy, 70f3288y, 70f3288hy ? general-purpose versions pd703264, 703264y, 703265, 703265y, 703265hy, 703266, 703266y, 703266hy, 70f3264, 70f3264y, 70f3266, 70f3266y, 70f3266hy ? iebus controller versions pd703274, 703274y, 703275, 703275y, 703275hy, 703276, 703276y, 703276hy, 70f3274, 70f3274y, 70f3276, 70f3276y, 70f3276hy ? can controller versions pd703284, 703284y, 703285, 703285y, 703285hy, 703286, 703286y, 703286hy, 70f3284, 70f3284y, 70f3286, 70f3286y, 70f3286hy, 703287, 703287y, 7 03287hy, 703288, 703288y, 703288hy, 70f3288, 70f3288y, 70f3288hy ? can controller (2-channel) versions pd703287, 703287y, 703287hy, 703288, 703288y , 703288hy, 70f3288, 70f3288y, 70f3288hy chapter 1 introduction user?s manual u16603ej5v1ud 25 table 1-2. v850es/sg2, v850es/sg2-h product list rom maskable interrupts function part number type size ram size operating frequency (max.) i 2 c iebus can external internal non-maskable interrupts pd703260 none pd703260y 256 kb 24 kb on-chip pd703261 none pd703261y mask rom on-chip pd70f3261 none pd70f3261y flash memory 384 kb 32 kb on-chip pd703262 none pd703262y 20 mhz 47 pd703262hy 512 kb 40 kb 32 mhz on-chip 46 pd703263 none pd703263y 20 mhz 47 pd703263hy mask rom 32 mhz on-chip 46 pd70f3263 none pd70f3263y 20 mhz 47 pd70f3263hy flash memory 640 kb 48 kb 32 mhz on-chip none 46 pd703270 none pd703270y 256 kb 24 kb on-chip pd703271 none pd703271y mask rom on-chip pd70f3271 none pd70f3271y flash memory 384 kb 32 kb on-chip pd703272 none pd703272y 20 mhz 51 pd703272hy 512 kb 40 kb 32 mhz on-chip 50 pd703273 none pd703273y 20 mhz 51 pd703273hy mask rom 32 mhz on-chip 50 pd70f3273 none pd70f3273y 20 mhz 51 pd70f3273hy flash memory 640 kb 48 kb 32 mhz on-chip on-chip none 50 pd703280 none pd703280y 256 kb 24 kb on-chip pd703281 none pd703281y mask rom on-chip pd70f3281 none pd70f3281y flash memory 384 kb 32 kb on-chip pd703282 none pd703282y 20 mhz 51 pd703282hy 512 kb 40 kb 32 mhz on-chip 50 pd703283 none pd703283y 20 mhz 51 pd703283hy mask rom 32 mhz on-chip 50 pd70f3283 none pd70f3283y 20 mhz 51 pd70f3283hy flash memory 640 kb 48 kb 32 mhz on-chip none on-chip 8 50 2 chapter 1 introduction user?s manual u16603ej5v1ud 26 1.2 features { minimum instruction execution time: v850es/sj2: 50 ns (operating with main clock (f xx ) = 20 mhz) v850es/sj2-h: 31.25 ns (operating with main clock (f xx ) = 32 mhz) { general-purpose registers: 32 bits 32 registers { cpu features: signed multiplication (16 16 32): 1 to 2 clocks signed multiplication (32 32 64): 1 to 5 clocks saturated operations (overflow and underflow detection functions included) 32-bit shift instruction: 1 clock bit manipulation instructions load/store instructions with long/short format { memory space: 64 mb of linear address space (for programs and data) external expansion: up to 16 mb ? internal memory: ram: 32/40/48 kb (see table 1-1 ) mask rom: 384/512/640 kb (see table 1-1 ) flash memory: 384/640 kb (see table 1-1 ) ? external bus interface: separate bus/multiplexed bus output selectable 8/16 bit data bus sizing function wait function ? programmable wait function ? external wait function idle state function bus hold function { interrupts and exceptions: non-maskable interrupts: 2 sources maskable interrupts: 59/ 60/63/64/67/68 sources (see table 1-1 ) software exceptions: 32 sources exception trap: 2 sources { i/o lines: i/o ports: 128 { timer function: 16-bit interv al timer m (tmm): 1 channel 16-bit timer/event counter p (tmp): 9 channels 16-bit timer/event counter q (tmq): 1 channel watch timer: 1 channel watchdog timer: 1 channel { real-time output port: 6 bits 2 channels { serial interface: asynchronous serial interface a (uarta) 3-wire variable-length serial interface b (csib) i 2 c bus interface (i 2 c) (i 2 c bus versions (y products) only) uarta/csib: 1 channel uarta/i 2 c: 2 channels csib/i 2 c: 1 channel csib: 4 channels uarta: 1 channel { iebus controller: 1 channel (iebus controller versions only) { can controller: 1 channel/2 channels (can controller versions only) { a/d converter: 10-bit resolution: 16 channels { d/a converter: 8-bit resolution: 2 channels { dma controller: 4 channels chapter 1 introduction user?s manual u16603ej5v1ud 27 { crc function: 16-bit error detection codes are generated for data in 8-bit units { on-chip debug function: jtag interface (flash memory version only) { rom correction: 4 correct ion addresses specifiable { clock generator: during main clock or subclock operation 7-level cpu clock (f xx , f xx /2, f xx /4, f xx /8, f xx /16, f xx /32, f xt ) clock-through mode/pll mode selectable { internal oscillation clock: 200 khz (typ.) { power-save functions: halt/idle1/idle2/stop/subclock/sub-idle mode { package: 144-pin plastic lqfp (fine pitch) (20 20) 1.3 application fields audio, car audio, consumer devices chapter 1 introduction user?s manual u16603ej5v1ud 28 1.4 ordering information (1) v850es/sj2 part number package internal rom pd703264gj-xxx-uen-a pd703264ygj-xxx-uen-a pd703265gj-xxx-uen-a pd703265ygj-xxx-uen-a pd703266gj-xxx-uen-a pd703266ygj-xxx-uen-a pd703274gj-xxx-uen-a pd703274ygj-xxx-uen-a pd703275gj-xxx-uen-a pd703275ygj-xxx-uen-a pd703276gj-xxx-uen-a pd703276ygj-xxx-uen-a pd703284gj-xxx-uen-a pd703284ygj-xxx-uen-a pd703285gj-xxx-uen-a pd703285ygj-xxx-uen-a pd703286gj-xxx-uen-a pd703286ygj-xxx-uen-a pd703287gj-xxx-uen-a pd703287ygj-xxx-uen-a pd703288gj-xxx-uen-a pd703288ygj-xxx-uen-a pd70f3264gj-uen-a pd70f3264ygj-uen-a pd70f3266gj-uen-a pd70f3266ygj-uen-a pd70f3274gj-uen-a pd70f3274ygj-uen-a pd70f3276gj-uen-a pd70f3276ygj-uen-a pd70f3284gj-uen-a pd70f3284ygj-uen-a pd70f3286gj-uen-a pd70f3286ygj-uen-a pd70f3288gj-uen-a pd70f3288ygj-uen-a 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 384 kb (mask rom) 384 kb (mask rom) 512 kb (mask rom) 512 kb (mask rom) 640 kb (mask rom) 640 kb (mask rom) 384 kb (mask rom) 384 kb (mask rom) 512 kb (mask rom) 512 kb (mask rom) 640 kb (mask rom) 640 kb (mask rom) 384 kb (mask rom) 384 kb (mask rom) 512 kb (mask rom) 512 kb (mask rom) 640 kb (mask rom) 640 kb (mask rom) 512 kb (mask rom) 512 kb (mask rom) 640 kb (mask rom) 640 kb (mask rom) 384 kb (flash memory) 384 kb (flash memory) 640 kb (flash memory) 640 kb (flash memory) 384 kb (flash memory) 384 kb (flash memory) 640 kb (flash memory) 640 kb (flash memory) 384 kb (flash memory) 384 kb (flash memory) 640 kb (flash memory) 640 kb (flash memory) 640 kb (flash memory) 640 kb (flash memory) remarks 1. xxx indicates rom code suffix. 2. v850es/sj2 microcontrollers are lead-free products. chapter 1 introduction user?s manual u16603ej5v1ud 29 (2) v850es/sj2-h part number package internal rom pd703265hygj-xxx-uen-a pd703266hygj-xxx-uen-a pd70f3266hygj-uen-a pd703275hygj-xxx-uen-a pd703276hygj-xxx-uen-a pd70f3276hygj-uen-a pd703285hygj-xxx-uen-a pd703286hygj-xxx-uen-a pd703287hygj-xxx-uen-a pd703288hygj-xxx-uen-a pd70f3286hygj-uen-a pd70f3288hygj-uen-a 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 144-pin plastic lqfp (fine pitch) (20 20) 512 kb (mask rom) 640 kb (mask rom) 640 kb (flash memory) 512 kb (mask rom) 640 kb (mask rom) 640 kb (flash memory) 512 kb (mask rom) 640 kb (mask rom) 512 kb (mask rom) 640 kb (mask rom) 640 kb (flash memory) 640 kb (flash memory) remarks 1. xxx indicates rom code suffix. 2. v850es/sj2 microcontrollers are lead-free products. chapter 1 introduction user?s manual u16603ej5v1ud 30 1.5 pin configuration (top view) 144-pin plastic lqfp (fine pitch) (20 20) ? v850es/sj2 pd703264gj-xxx-uen-a pd703275gj-xxx-uen-a pd703286gj-xxx-uen-a pd703264ygj-xxx-uen-a pd703275ygj-xxx-uen-a pd703286ygj-xxx-uen-a pd703265gj-xxx-uen-a pd703276gj-xxx-uen-a pd703287gj-xxx-uen-a pd703265ygj-xxx-uen-a pd703276ygj-xxx-uen-a pd703287ygj-xxx-uen-a pd703266gj-xxx-uen-a pd70f3274gj-uen-a pd703288gj-xxx-uen-a pd703266ygj-xxx-uen-a pd70f3274ygj-uen-a pd703288ygj-xxx-uen-a pd70f3264gj-uen-a pd70f3276gj-uen-a pd70f3284gj-uen-a pd70f3264ygj-uen-a pd70f3276ygj-uen-a pd70f3284ygj-uen-a pd70f3266gj-uen-a pd703284gj-xxx-uen-a pd70f3286gj-uen-a pd70f3266ygj-uen-a pd703284ygj-xxx-uen-a pd70f3286ygj-uen-a pd703274gj-xxx-uen-a pd703285gj-xxx-uen-a pd70f3288gj-uen-a pd703274ygj-xxx-uen-a pd703285ygj-xxx-uen-a pd70f3288ygj-uen-a ? v850es/sj2-h pd703265hygj-xxx-uen-a pd703276hygj-xxx-uen-a pd703287hygj-xxx-uen-a pd703266hygj-xxx-uen-a pd70f3276hygj-uen-a pd703288hygj-xxx-uen-a pd70f3266hygj-uen-a pd703285hygj-xxx-uen-a pd70f3286hygj-uen-a pd703275hygj-xxx-uen-a pd703286hygj-xxx-uen-a pd70f3288hygj-uen-a chapter 1 introduction user?s manual u16603ej5v1ud 31 pdl3/ad3 pdl2/ad2 pdl1/ad1 pdl0/ad0 bv dd bv ss pct7 pct6/astb pct5 pct4/rd pct3 pct2 pct1/wr1 pct0/wr0 pcs7 pcs6 pcs5 pcs4 pcm5 pcm4 pcm3/hldrq pcm2/hldak pcm1/clkout pcm0/wait pcs3/cs3 pcs2/cs2 pcs1/cs1 pcs0/cs0 pcd3 pcd2 pcd1 pcd0 p915/a15 note 9 /intp6/tip50/top50 p914/a14 note 9 /intp5/tip51/top51 p913/a13 note 9 /intp4 p912/a12 note 9 /sckb3 av ref0 av ss p10/ano0 p11/ano1 av ref1 p00/tip61/top61 p01/tip60/top60 ic note 1 /flmd0 note 1 v dd regc note 2 v ss x1 x2 reset xt1 xt2 p02/nmi p03/intp0/adtrg p04/intp1 p05/intp2/drst notes 3, 4 p06/intp3 p40/sib0/sda01 note 5 p41/sob0/scl01 note 5 p42/sckb0 p30/txda0/sob4 p31/rxda0/intp7/sib4 p32/ascka0/sckb4/tip00/top00 p33/tip01/top01/ctxd1 note 6 p34/tip10/top10/crxd1 note 6 p35/tip11/top11 p36/ietx0 note 7 /ctxd0 note 8 p37/ierx0 note 7 /crxd0 note 8 ev ss ev dd p38/txda2/sda00 note 5 p39/rxda2/scl00 note 5 p50/tiq01/kr0/toq01/rtp00 p51/tiq02/kr1/toq02/rtp01 p52/tiq03/kr2/toq03/rtp02/ddi note 3 p53/sib2/kr3/tiq00/toq00/rtp03/ddo note 3 p54/sob2/kr4/rtp04/dck note 3 p55/sckb2/kr5/rtp05/dms note 3 p60/rtp10 p61/rtp11 p62/rtp12 p63/rtp13 p64/rtp14 p65/rtp15 p66/sib5 p67/sob5 p68/sckb5 p69/tip70/top70 p610/tip71 p611/top71 p612/tip80/top80 p613/tip81/top81 p614 p615 p80/rxda3/intp8 p81/txda3 p90/a0 note 9 /kr6/txda1/sda02 note 5 p91/a1 note 9 /kr7/rxda1/scl02 note 5 p92/a2 note 9 /tip41/top41 p93/a3 note 9 /tip40/top40 p94/a4 note 9 /tip31/top31 p95/a5 note 9 /tip30/top30 p96/a6 note 9 /tip21/top21 p97/a7 note 9 /sib1/tip20/top20 p98/a8 note 9 /sob1 p99/a9 note 9 /sckb1 p910/a10 note 9 /sib3 p911a11 note 9 /sob3 p70/ani0 note 10 p71/ani1 note 10 p72/ani2 note 10 p73/ani3 note 10 p74/ani4 note 10 p75/ani5 note 10 p76/ani6 note 10 p77/ani7 note 10 p78/ani8 note 10 p79/ani9 note 10 p710/ani10 note 10 p711/ani11 note 10 p712/ani12 note 10 p713/ani13 note 10 p714/ani14 note 10 p715/ani15 note 10 pdh7/a23 pdh6/a22 pdh5/a21 pdh4/a20 pdh3/a19 pdh2/a18 pdh1/a17 pdh0/a16 pdl15/ad15 pdl14/ad14 pdl13/ad13 pdl12/ad12 pdl11/ad11 pdl10/ad10 pdl9/ad9 pdl8/ad8 pdl7/ad7 pdl6/ad6 pdl5/ad5/flmd1 note 1 pdl4/ad4 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 notes 1. ic: directly connect this pin to v ss (mask rom version only). flmd0: connect these pins to v ss in the normal mode (flash memory version only). flmd1: flash memory version only 2. connect the regc pin to v ss via a 4.7 f capacitor. 3. the drst, ddi, ddo, dck, and dms pins are valid only in the flash memory version. 4. fix this pin to the low level from when the rese t status has been released until the ocdm.ocdm0 bit is cleared (0) when the on-chip debug func tion is not used. for details, see 4.6.3 cautions on on-chip debug pins . 5. the scl00 to scl02 and sda00 to sda02 pins are valid only in the i 2 c bus version (y product). 6. the ctxd1 and crxd1 pins are valid only in the can controller (2-channel) version. 7. the ietx0 and ierx0 pins are valid only in the iebus controller version. 8. the ctxd0 and crxd0 pins are vali d only in the can controller version. 9. port 9 cannot be used as port pins or other alternat e-function pins when the a0 to a15 pins are used in the separate bus mode. 10. to use port 7 (p70/ani0 to p715/ani15) as a/d conv erter function pins and port i/o pins in mix, be sure to observe usage cautions (see 13.6 (4) alternate i/o ). chapter 1 introduction user?s manual u16603ej5v1ud 32 pin names a0 to a23: ad0 to ad15: adtrg: ani0 to ani15: ano0, ano1: ascka0: astb: av ref0 , av ref1 : av ss : bv dd : bv ss : clkout: crxd0, crxd1: cs0 to cs3: ctxd0, ctxd1: dck: ddi: ddo: dms: drst: ev dd : ev ss : flmd0, flmd1: hldak: hldrq: ic: ierx0: ietx0: intp0 to intp8: kr0 to kr7: nmi: p00 to p06: p10, p11: p30 to p39: p40 to p42: p50 to p55: p60 to p615: p70 to p715: p80, p81: p90 to p915: pcd0 to pcd3: pcm0 to pcm5: pcs0 to pcs7: address bus address/data bus a/d trigger input analog input analog output asynchronous serial clock address strobe analog reference voltage analog v ss power supply for bus interface ground for bus interface clock output can receive data chip select can transmit data debug clock debug data input debug data output debug mode select debug reset power supply for port ground for port flash programming mode hold acknowledge hold request internally connected iebus receive data iebus transmit data external interrupt input key return non-maskable interrupt request port 0 port 1 port 3 port 4 port 5 port 6 port 7 port 8 port 9 port cd port cm port cs pct0 to pct7: pdh0 to pdh7: pdl0 to pdl15: rd: regc: reset: rtp00 to rtp05, rtp10 to rtp15: rxda0 to rxda3: sckb0 to sckb5: scl00 to scl02: sda00 to sda02: sib0 to sib5: sob0 to sob5: tip00, tip01, tip10, tip11, tip20, tip21, tip30, tip31, tip40, tip41, tip50, tip51, tip60, tip61, tip70, tip71, tip80, tip81, tiq00 to tiq03: top00, top01, top10, top11, top20, top21, top30, top31, top40, top41, top50, top51, top60, top61, top70, top71, top80, top81, toq00 to toq03: txda0 to txda3: v dd: v ss: wait: wr0: wr1: x1, x2: xt1, xt2: port ct port dh port dl read strobe regulator control reset real-time output port receive data serial clock serial clock serial data serial input serial output timer input timer output transmit data power supply ground wait lower byte write strobe upper byte write strobe crystal for main clock crystal for subclock chapter 1 introduction user?s manual u16603ej5v1ud 33 1.6 function block configuration 1.6.1 internal block diagram nmi toq00 to toq03 tiq00 to tiq03 rtp00 to rtp05, rtp10 to rtp15 sob0/scl01 note 3 sib0/sda01 note 3 sckb0 intp0 to intp8 intc 16-bit timer/ counter q: 1 ch top00 to top80, top01 to top81 tip00 to tip80, tip01 to tip81 16-bit timer/ counter p: 9 ch kr0 to kr7 rto iebus note 6 csib1 to csib3, csib5 dmac watchdog timer 2 watch timer key return function note 1 note 2 ram rom pc general-purpose registers 32 bits 32 multiplier 16 16 32 alu system registers 32-bit barrel shifter cpu hldrq hldak astb rd wait wr0, wr1 a0 to a23 ad0 to ad15 ic note 4 /flmd0 note 5 flmd1 note 5 ports cg regulator pll lvi note 9 internal oscillator clm cs0 to cs3 pcs0 to pcs7 pcm0 to pcm5 pct0 to pct7 pdh0 to pdh7 pdl0 to pdl15 pcd0 to pcd3 p90 to p915 p80, p81 p70 to p715 p60 to p615 p50 to p55 p40 to p42 p30 to p39 p10, p11 p00 to p06 av ref1 ano0, ano1 ani0 to ani15 av ss av ref0 adtrg clkout xt1 xt2 x1 x2 reset v dd v ss regc bv dd bv ss ev dd ev ss instruction queue bcu sob1 to sob3, sob5 sib1 to sib3, sib5 sckb1 to sckb3, sckb5 txda0/sob4 rxda0/sib4 ascka0/sckb4 txda2/sda00 note 3 rxda2/scl00 note 3 ietx0 note 6 ierx0 note 6 csib0 i 2 c01 note 3 rom correction 16-bit interval timer m: 1 ch uarta0 csib4 uarta2 i 2 c00 note 3 txda3 rxda3 uarta3 txda1/sda02 note 3 rxda1/scl02 note 3 uarta1 i 2 c02 note 3 on-chip debug funtion note 5 drst note 5 dms note 5 ddi note 5 dck note 5 ddo note 5 a/d converter d/a converter can0 note 7 , can1 note 8 ctxd0 note 7 , ctxd1 note 8 crxd0 note 7 , crxd1 note 8 notes 1. 384/512/640 kb (mask rom) (see table 1-1 ) 384/640 kb (flash memory) (see table 1-1 ) 2. 32/40/48 kb (see table 1-1 ) 3. i 2 c bus versions (y products) only 4. mask rom versions only 5. flash memory versions only 6. iebus controller versions only 7. can controller versions only 8. can controller (2-channel) versions only 9. v850es/sj2 only chapter 1 introduction user?s manual u16603ej5v1ud 34 1.6.2 internal units (1) cpu the cpu uses five-stage pipeline control to enable single -clock execution of addres s calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. other dedicated on-chip hardware, such as a multiplier (16 bits 16 bits 32 bits) and a barrel shifter (32 bits) contribute to faster complex processing. (2) bus control unit (bcu) the bcu starts a required external bus cycle based on the physical address obtai ned by the cpu. when an instruction is fetched from external memory space a nd the cpu does not send a bus cycle start request, the bcu generates a prefetch address and prefetches the instruction code. the pref etched instruction code is stored in an instruction queue. (3) rom this is a 640/512/384 kb mask rom or flash memory mapped to addresses 0000000h to 009ffffh/0000000h to 007ffffh/0000000h to 005ffffh. it can be accessed from the cpu in one clock during instruction fetch. (4) ram this is a 48/40/32 kb ram mapped to addresses 3ff3000h to 3ffefffh/3ff5000h to 3ffefffh/3ff7000h to 3ffefffh. it can be accessed from the cpu in one clock during data access. (5) interrupt controller (intc) this controller handles hardware interrupt requests (nmi, intp0 to intp8) from on-chip peripheral hardware and external hardware. eight levels of interrupt priorities can be specified for these interrupt requests, and multiplexed servicing control can be performed. (6) clock generator (cg) a main clock oscillator and subclock oscillator are pr ovided and generate the main clock oscillation frequency (f x ) and subclock frequency (f xt ), respectively. there are two modes in the clock-through mode, f x is used as the main clock frequency (f xx ) as is. in the pll mode, f x is used multiplied by 4 or 8. the cpu clock frequency (f cpu ) can be selected from among f xx , f xx /2, f xx /4, f xx /8, f xx /16, f xx /32, and f xt . (7) internal oscillator an internal oscillator is provided on chip. the oscillat ion frequency is 200 khz (typ). the internal oscillator supplies the clock for watchdog timer 2 and timer m. (8) timer/counter nine-channel 16-bit timer/event counter p (tmp), one- channel 16-bit timer/event counter q (tmq), and one- channel 16-bit interval timer m (tmm), are provided on chip. (9) watch timer this timer counts the reference time period (0.5 s) for counting the clock (the 32.768 khz subclock or the 32.768 khz clock f brg from prescaler 3). the watch timer can also be used as an interval timer for the main clock. chapter 1 introduction user?s manual u16603ej5v1ud 35 (10) watchdog timer 2 a watchdog timer is provided on chip to detect inadv ertent program loops, system abnormalities, etc. either the internal oscillation clock, the main clock, or the subclock can be selected as the source clock. watchdog timer 2 generates a non-maskable interrupt request signal (intwdt2) or a system reset signal (wdt2res) after an overflow occurs. (11) serial interface the v850es/sj2 and v850es/sj2-h includ e three kinds of serial interfaces asynchronous serial interface a (uarta), 3-wire variable-length serial interface b (csib), and an i 2 c bus interface (i 2 c). in the case of uarta, data is transferred via the txda0 to txda3 pins and rxda0 to rxda3 pins. in the case of csib, data is transferred via the sob0 to sob5 pins, sib0 to sib5 pins, and sckb0 to sckb5 pins. in the case of i 2 c, data is transferred via the sda00 to sda02 and scl00 to scl02 pins. the i 2 c is provided only in i 2 c bus versions (y products) (see table 1-1 ). (12) iebus controller the iebus controller is a small-scale digital data transmission system for transferring data between units. the iebus controller is provided only in iebus controller versions. (13) can controller the can controller is a small-scale digital data transmission system for transferring data between units. the can controller is provided only in can controller versions. (14) a/d converter this 10-bit a/d converter includes 16 analog input pins. conversion is performed using the successive approximation method. (15) d/a converter a two-channel, 8-bit-resolution d/a converter that uses the r-2r ladder method is provided on chip. (16) dma controller a 4-channel dma controller is provided on chip. this controller transfers data between the internal ram and on-chip peripheral i/o devices in resp onse to interrupt requests sent by on-chip peripheral i/o. (17) rom correction a rom correction function that replaces part of a program in the mask rom with a program in the internal ram is provided. up to four correction addresses can be specified. (18) key interrupt function a key interrupt request signal (intkr) can be generated by inputting a falling edge to the key input pins (8 channels). (19) real-time output function the real-time output function transfe rs preset 6-bit data to output la tches upon the occurrence of a timer compare register match signal. chapter 1 introduction user?s manual u16603ej5v1ud 36 (20) crc function a crc operation circuit that generates 16-bit crc (cycl ic redundancy check) code upon setting of 8-bit data is provided on chip. (21) on-chip debug function an on-chip debug function via an on-chip debug emulator that uses the jtag (joint test action group) communication specifications is provided. swit ching between the normal port function and on-chip debugging function is done with the control pi n input level and the ocdm register. the on-chip debug function is provided only in flash memory versions. (22) ports the following general-purpose port functions and control pin functions are available. port i/o alternate function p0 7-bit i/o timer i/o, nmi, external interrupt, a/d converter trigger, debug reset p1 2-bit i/o d/a converter analog output p3 10-bit i/o external interrupt, serial interface, timer i/o, can data i/o, iebus data i/o p4 3-bit i/o serial interface p5 6-bit i/o timer i/o, real-time output, key interrupt input, serial interface, debug i/o p6 16-bit i/o real-time output, serial interface, timer i/o p7 16-bit i/o a/d converter analog input p8 2-bit i/o serial interface, external interrupt p9 16-bit i/o external address bus, serial interface, key interrupt input, timer i/o, external interrupt pcd 4-bit i/o ? pcm 6-bit i/o external control signal pcs 8-bit i/o chip select output pct 8-bit i/o external control signal pdh 8-bit i/o external address bus pdl 16-bit i/o external address/data bus user?s manual u16603ej5v1ud 37 chapter 2 pin functions 2.1 list of pin functions the names and functions of the pins in the v 850es/sj2 and v850es/sj2-h are described below. there are four types of pin i/o buffer power supplies: av ref0 , av ref1 , bv dd , and ev dd . the relationship between these power supplies and the pins is described below. table 2-1. pin i/o buffer power supplies power supply corresponding pins av ref0 port 7 av ref1 port 1 bv dd ports cd, cm, cs, ct, dh, dl ev dd reset, ports 0, 3 to 6, 8, 9 chapter 2 pin functions user?s manual u16603ej5v1ud 38 (1) port pins (1/4) pin name pin no. i/o function alternate function p00 6 tip61/top61 p01 7 tip60/top60 p02 17 nmi p03 18 intp0/adtrg p04 19 intp1 p05 note 1 20 intp2/drst note 2 p06 21 i/o port 0 7-bit i/o port input/output can be specified in 1-bit units. n-ch open-drain output can be specified in 1-bit units. 5 v tolerant. intp3 p10 3 ano0 p11 4 i/o port 1 2-bit i/o port input/output can be specified in 1-bit units. ano1 p30 25 txda0/sob4 p31 26 rxda0/intp7/sib4 p32 27 ascka0/sckb4/tip00/top00 p33 28 tip01/top01/ctxd1 note 3 p34 29 tip10/top10/crxd1 note 3 p35 30 tip11/top11 p36 31 ctxd0 note 4 /ietx0 note 5 p37 32 crxd0 note 4 /ierx0 note 5 p38 35 txda2/sda00 note 6 p39 36 i/o port 3 10-bit i/o port input/output can be specified in 1-bit units. n-ch open-drain output can be specified in 1-bit units. 5 v tolerant. rxda2/scl00 note 6 p40 22 sib0/sda01 note 6 p41 23 sob0/scl01 note 6 p42 24 i/o port 4 3-bit i/o port input/output can be specified in 1-bit units. n-ch open-drain output can be specified in 1-bit units. 5 v tolerant. sckb0 p50 37 tiq01/kr0/toq01/rtp00 p51 38 tiq02/kr1/toq02/rtp01 p52 39 tiq03/kr2/toq03/rtp02/ddi note 2 p53 40 sib2/kr3/tiq00/toq00/rtp03/ ddo note 2 p54 41 sob2/kr4/rtp04/dck note 2 p55 42 i/o port 5 6-bit i/o port input/output can be specified in 1-bit units. n-ch open-drain output can be specified in 1-bit units. 5 v tolerant. sckb2/kr5/rtp05/dms note 2 notes 1. fix this pin to low level from when the reset status has been released unt il the ocdm.ocdm0 bit is cleared (0) when the on-chip debug function is not used. for details, see 4.6.3 cautions on on-chip debug pins . a pull-down resistor is incorporated. it can be disconnected by clearing the ocdm.ocdm0 bit to 0. 2. flash memory versions only 3. can controller (2-channel) versions only 4. can controller versions only 5. iebus controller versions only 6. i 2 c bus versions (y products) only chapter 2 pin functions user?s manual u16603ej5v1ud 39 (2/4) pin name pin no. i/o function alternate function p60 43 rtp10 p61 44 rtp11 p62 45 rtp12 p63 46 rtp13 p64 47 rtp14 p65 48 rtp15 p66 49 sib5 p67 50 sob5 p68 51 sckb5 p69 52 tip70/top70 p610 53 tip71 p611 54 top71 p612 55 tip80/top80 p613 56 tip81/top81 p614 57 ? p615 58 i/o port 6 16-bit i/o port input/output can be specified in 1-bit units. n-ch open-drain output can be specified in 1-bit units. 5 v tolerant. ? p70 144 ani0 p71 143 ani1 p72 142 ani2 p73 141 ani3 p74 140 ani4 p75 139 ani5 p76 138 ani6 p77 137 ani7 p78 136 ani8 p79 135 ani9 p710 134 ani10 p711 133 ani11 p712 132 ani12 p713 131 ani13 p714 130 ani14 p715 129 i/o port 7 16-bit i/o port input/output can be specified in 1-bit units. ani15 p80 59 rxda3/intp8 p81 60 i/o port 8 2-bit i/o port input/output can be specified in 1-bit units. n-ch open-drain output can be specified in 1-bit units. 5 v tolerant. txda3 chapter 2 pin functions user?s manual u16603ej5v1ud 40 (3/4) pin name pin no. i/o function alternate function p90 61 a0/kr6/txda1/sda02 note p91 62 a1/kr7/rxda1/scl02 note p92 63 a2/tip41/top41 p93 64 a3/tip40/top40 p94 65 a4/tip31/top31 p95 66 a5/tip30/top30 p96 67 a6/tip21/top21 p97 68 a7/sib1/tip20/top20 p98 69 a8/sob1 p99 70 a9/sckb1 p910 71 a10/sib3 p911 72 a11/sob3 p912 73 a12/sckb3 p913 74 a13/intp4 p914 75 a14/intp5/tip51/top51 p915 76 i/o port 9 16-bit i/o port input/output can be specified in 1-bit units. n-ch open-drain output can be specified in 1-bit units. 5 v tolerant. a15/intp6/tip50/top50 pcd0 77 ? pcd1 78 ? pcd2 79 ? pcd3 80 i/o port cd 4-bit i/o port input/output can be specified in 1-bit units. ? pcm0 85 wait pcm1 86 clkout pcm2 87 hldak pcm3 88 hldrq pcm4 89 ? pcm5 90 i/o port cm 6-bit i/o port input/output can be specified in 1-bit units. ? pcs0 81 cs0 pcs1 82 cs1 pcs2 83 cs2 pcs3 84 cs3 pcs4 91 ? pcs5 92 ? pcs6 93 ? pcs7 94 i/o port cs 8-bit i/o port input/output can be specified in 1-bit units. ? note i 2 c bus versions (y products) only chapter 2 pin functions user?s manual u16603ej5v1ud 41 (4/4) pin name pin no. i/o function alternate function pct0 95 wr0 pct1 96 wr1 pct2 97 ? pct3 98 ? pct4 99 rd pct5 100 ? pct6 101 astb pct7 102 i/o port ct 8-bit i/o port input/output can be specified in 1-bit units. ? pdh0 121 a16 pdh1 122 a17 pdh2 123 a18 pdh3 124 a19 pdh4 125 a20 pdh5 126 a21 pdh6 127 a22 pdh7 128 i/o port dh 8-bit i/o port input/output can be specified in 1-bit units. a23 pdl0 105 ad0 pdl1 106 ad1 pdl2 107 ad2 pdl3 108 ad3 pdl4 109 ad4 pdl5 110 ad5/flmd1 note pdl6 111 ad6 pdl7 112 ad7 pdl8 113 ad8 pdl9 114 ad9 pdl10 115 ad10 pdl11 116 ad11 pdl12 117 ad12 pdl13 118 ad13 pdl14 119 ad14 pdl15 120 i/o port dl 16-bit i/o port input/output can be specified in 1-bit units. ad15 note flash memory versions only chapter 2 pin functions user?s manual u16603ej5v1ud 42 (2) non-port pins (1/7) pin name pin no. i/o function alternate function a0 61 p90/kr6/txda1/sda02 note 1 a1 62 p91/kr7/rxda1/scl02 note 1 a2 63 p92/tip41/top41 a3 64 p93/tip40/top40 a4 65 p94/tip31/top31 a5 66 p95/tip30/top30 a6 67 p96/tip21/top21 a7 68 p97/sib1/tip20/top20 a8 69 p98/sob1 a9 70 p99/sckb1 a10 71 p910/sib3 a11 72 p911/sob3 a12 73 p912/sckb3 a13 74 p913/intp4 a14 75 p914/intp5/tip51/top51 a15 76 output address bus for external memory (when using separate bus) port 9 cannot be used as port pins or other alternate- function pins when the a0 to a15 pins are used in the separate bus mode. n-ch open-drain output selectable. 5 v tolerant. p915/intp6/tip50/top50 a16 121 pdh0 a17 122 pdh1 a18 123 pdh2 a19 124 pdh3 a20 125 pdh4 a21 126 pdh5 a22 127 pdh6 a23 128 output address bus for external memory pdh7 ad0 105 pdl0 ad1 106 pdl1 ad2 107 pdl2 ad3 108 pdl3 ad4 109 pdl4 ad5 110 pdl5/flmd1 note 2 ad6 111 pdl6 ad7 112 pdl7 ad8 113 pdl8 ad9 114 pdl9 ad10 115 pdl10 ad11 116 pdl11 ad12 117 pdl12 ad13 118 pdl13 ad14 119 pdl14 ad15 120 i/o address bus/data bus for external memory pdl15 notes 1. i 2 c bus versions (y products) only 2. flash memory versions only chapter 2 pin functions user?s manual u16603ej5v1ud 43 (2/7) pin name pin no. i/o function alternate function adtrg 18 input a/d converter external trigger input. 5 v tolerant. p03/intp0 ani0 144 p70 ani1 143 p71 ani2 142 p72 ani3 141 p73 ani4 140 p74 ani5 139 p75 ani6 138 p76 ani7 137 p77 ani8 136 p78 ani9 135 p79 ani10 134 p710 ani11 133 p711 ani12 132 p712 ani13 131 p713 ani14 130 p714 ani15 129 input analog voltage input for a/d converter p715 ano0 3 p10 ano1 4 output analog voltage output for d/a converter p11 ascka0 27 input uarta0 baud rate clock input. 5 v tolerant. p32/sckb4/tip00/top00 astb 101 output address strobe signal output for external memory pct6 av ref0 1 reference voltage input for a/d converter/positive power supply for port 7 ? av ref1 5 ? reference voltage input for d/a converter/positive power supply for port 1 ? av ss 2 ? ground potential for a/d and d/a converters (same potential as v ss ) ? bv dd 104 ? positive power supply pin for bus interface and alternate- function ports ? bv ss 103 ? ground potential for bus interface and alternate-function ports ? clkout 86 output internal system clock output pcm1 crxd0 note 1 32 p37/ierx0 note 2 crxd1 note 3 29 input can receive data input. 5 v tolerant. p34/tip10/top10 cs0 81 pcs0 cs1 82 pcs1 cs2 83 pcs2 cs3 84 output chip select output pcs3 ctxd0 note 1 31 p36/ietx0 note 2 ctxd1 note 3 28 output can0 and can1 transmit data output. n-ch open-drain output selectable. 5 v tolerant. p33/tip01/top01 notes 1. can controller versions only 2. iebus controller versions only 3. can controller (2-channel) versions only chapter 2 pin functions user?s manual u16603ej5v1ud 44 (3/7) pin name pin no. i/o function alternate function dck note 1 41 input debug clock input. 5 v tolerant. p54/sob2/kr4/rtp04 ddi note 1 39 input debug data input. 5 v tolerant. p52/tiq03/kr2/toq03/rtp02 ddo notes 1, 2 40 output debug data output. n-ch open-drain output selectable. 5 v tolerant. p53/sib2/kr3/tiq00/toq00/ rtp03 dms note 1 42 input debug mode select input. 5 v tolerant. p55/sckb2/kr5/rtp05 drst note 1 20 input debug reset input. 5 v tolerant. p05/intp2 ev dd 34 ? positive power supply for external (same potential as v dd ) ? ev ss 33 ? ground potential for external (same potential as v ss ) ? flmd0 note 1 8 ? flmd1 note 1 110 input flash memory programming mode setting pin pdl5/ad5 hldak 87 output bus hold acknowledge output pcm2 hldrq 88 input bus hold request input pcm3 ic note 3 8 ? internally connected ? ierx0 note 4 32 input iebus receive data input. 5 v tolerant. p37/crxd0 note 5 ietx0 note 4 31 output iebus transmit data output. n-ch open-drain output selectable. 5 v tolerant. p36/ctxd0 note 5 intp0 18 p03/adtrg intp1 19 p04 intp2 20 p05/drst note 1 intp3 21 p06 intp4 74 p913/a13 intp5 75 p914/a14/tip51/top51 intp6 76 p915/a15/tip50/top50 intp7 26 p31/rxda0/sib4 intp8 59 input external interrupt request input (maskable, analog noise elimination). analog noise elimination or digital noise elimination selectable for intp3 pin. 5 v tolerant. p80/rxda3 kr0 note 6 37 p50/tiq01/toq01/rtp00 kr1 note 6 38 p51/tiq02/toq02/rtp01 kr2 note 6 39 p52/tiq03/toq03/ rtp02/ddi note 1 kr3 note 6 40 p53/sib2/tiq00/toq00/ rtp03/ddo note 1 kr4 note 6 41 p54/sob2/rtp04/dck note 1 kr5 note 6 42 p55/sckb2/rtp05/dms note 1 kr6 note 6 61 p90/a0/txda1/sda02 note 7 kr7 note 6 62 input key interrupt input (on-chip analog noise eliminator). 5 v tolerant. p91/a1/rxda1/scl02 note 7 notes 1. flash memory versions only 2. in the on-chip debug mode, high-level output is forcibly set. 3. mask rom versions only 4. iebus controller versions only 5. can controller versions only 6. pull this pin up externally. 7. i 2 c bus versions (y products) only chapter 2 pin functions user?s manual u16603ej5v1ud 45 (4/7) pin name pin no. i/o function alternate function nmi note 1 17 input external interrupt input (non-maskable, analog noise elimination). 5 v tolerant. p02 rd 99 output read strobe signal output for external memory pct4 regc 10 ? connection of regulator output stabilization capacitance (4.7 f) ? reset 14 input system reset input ? rtp00 37 p50/tiq01/kr0/toq01 rtp01 38 p51/tiq02/kr1/toq02 rtp02 39 p52/tiq03/kr2/toq03/ddi note 2 rtp03 40 p53/sib2/kr3/tiq00/toq00/ ddo note 2 rtp04 41 p54/sob2/kr4/dck note 2 rtp05 42 p55/sckb2/kr5/dms note 2 rtp10 43 p60 rtp11 44 p61 rtp12 45 p62 rtp13 46 p63 rtp14 47 p64 rtp15 48 output real-time output port. n-ch open-drain output selectable. 5 v tolerant. p65 rxda0 26 p31/intp7/sib4 rxda1 62 p91/a1/kr7/scl02 note 3 rxda2 36 p39/scl00 note 3 rxda3 59 input serial receive data input (uarta0 to uarta3) 5 v tolerant. p80/intp8 sckb0 24 p42 sckb1 70 p99/a9 sckb2 42 p55/kr5/rtp05/dms note 2 sckb3 73 p912/a12 sckb4 27 p32/ascka0/tip00/top00 sckb5 51 i/o serial clock i/o (csib0 to csib5) n-ch open-drain output selectable. 5 v tolerant. p68 scl00 note 3 36 p39/rxda2 scl01 note 3 23 p41/sob0 scl02 note 3 62 i/o serial clock i/o (i 2 c00 to i 2 c02) n-ch open-drain output selectable. 5 v tolerant. p91/a1/kr7/rxda1 sda00 note 3 35 p38/txda2 sda01 note 3 22 p40/sib0 sda02 note 3 61 i/o serial transmit/receive data i/o (i 2 c00 to i 2 c02) n-ch open-drain output selectable. 5 v tolerant. p90/a0/kr6/txda1 notes 1. the nmi pin alternately functions as the p02 pin. it f unctions as the p02 pin after reset. to enable the nmi pin, set the pmc0.pmc02 bit to 1. the initial setting of the nmi pin is ?no edge detected?. select the nmi pin valid edge using intf0 and intr0 registers. 2. flash memory versions only 3. i 2 c bus versions (y products) only chapter 2 pin functions user?s manual u16603ej5v1ud 46 (5/7) pin name pin no. i/o function alternate function sib0 22 p40/sda01 note 1 sib1 68 p97/a7/tip20/top20 sib2 40 p53/kr3/tiq00/toq00/rtp03/ ddo note 2 sib3 71 p910/a10 sib4 26 p31/rxda0/intp7 sib5 49 input serial receive data input (csib0 to csib5) 5 v tolerant. p66 sob0 23 p41/scl01 note 1 sob1 69 p98/a8 sob2 41 p54/kr4/rtp04/dck note 2 sob3 72 p911/a11 sob4 25 p30/txda0 sob5 50 output serial transmit data output (csib0 to csib5) n-ch open-drain output selectable. 5 v tolerant. p67 tip00 27 external event count input/capture trigger input/external trigger input (tmp0). 5 v tolerant. p32/ascka0/sckb4/top00 tip01 28 capture trigger input (tmp0). 5 v tolerant. p33/top01/ctxd1 note 3 tip10 29 external event count input/capture trigger input/external trigger input (tmp1). 5 v tolerant. p34/top10/crxd1 note 3 tip11 30 capture trigger input (tmp1). 5 v tolerant. p35/top11 tip20 68 external event count input/capture trigger input/external trigger input (tmp2). 5 v tolerant. p97/a7/sib1/top20 tip21 67 capture trigger input (tmp2). 5 v tolerant. p96/a6/top21 tip30 66 external event count input/capture trigger input/external trigger input (tmp3). 5 v tolerant. p95/a5/top30 tip31 65 capture trigger input (tmp3). 5 v tolerant. p94/a4/top31 tip40 64 external event count input/capture trigger input/external trigger input (tmp4). 5 v tolerant. p93/a3/top40 tip41 63 input capture trigger input (tmp4). 5 v tolerant. p92/a2/top41 notes 1. i 2 c bus versions (y products) only 2. flash memory versions only 3. can controller (2-channel) versions only chapter 2 pin functions user?s manual u16603ej5v1ud 47 (6/7) pin name pin no. i/o function alternate function tip50 76 external event count input/capture trigger input/external trigger input (tmp5). 5 v tolerant. p915/a15/intp6/top50 tip51 75 capture trigger input (tmp5). 5 v tolerant. p914/a14/intp5/top51 tip60 7 external event count input/capture trigger input/external trigger input (tmp6). 5 v tolerant. p01/top60 tip61 6 capture trigger input (tmp6). 5 v tolerant. p00/top61 tip70 52 external event count input/capture trigger input/external trigger input (tmp7). 5 v tolerant. p69/top70 tip71 53 capture trigger input (tmp7). 5 v tolerant. p610 tip80 55 external event count input/capture trigger input/external trigger input (tmp8). 5 v tolerant. p612/top80 tip81 56 input capture trigger input (tmp8). 5 v tolerant. p613/top81 tiq00 40 external event count input/capture trigger input/external trigger input (tmq0). 5 v tolerant. p53/sib2/kr3/toq00/rtp03/ ddo note 1 tiq01 37 p50/kr0/toq01/rtp00 tiq02 38 p51/kr1/toq02/rtp01 tiq03 39 input capture trigger input (tmq0). 5 v tolerant. p52/kr2/toq03/rtp02/ddi note 1 top00 27 p32/ascka0/sckb4/tip00 top01 28 timer output (tmp0) n-ch open-drain output selectable. 5 v tolerant. p33/tip01/ctxd1 note 2 top10 29 p34/tip10/crxd1 note 2 top11 30 timer output (tmp1) n-ch open-drain output selectable. 5 v tolerant. p35/tip11 top20 68 p97/a7/sib1/tip20 top21 67 timer output (tmp2) n-ch open-drain output selectable. 5 v tolerant. p96/a6/tip21 top30 66 p95/a5/tip30 top31 65 timer output (tmp3) n-ch open-drain output selectable. 5 v tolerant. p94/a4/tip31 top40 64 p93/a3/tip40 top41 63 timer output (tmp4) n-ch open-drain output selectable. 5 v tolerant. p92/a2/tip41 top50 76 p915/a15/intp6/tip50 top51 75 timer output (tmp5) n-ch open-drain output selectable. 5 v tolerant. p914/a14/intp5/tip51 top60 7 p01/tip60 top61 6 output timer output (tmp6) n-ch open-drain output selectable. 5 v tolerant. p00/tip61 notes 1. flash memory versions only 2. can controller (2-channel) versions only chapter 2 pin functions user?s manual u16603ej5v1ud 48 (7/7) pin name pin no. i/o function alternate function top70 52 p69/tip70 top71 54 timer output (tmp7) n-ch open-drain output selectable. 5 v tolerant. p611 top80 55 p612/tip80 top81 56 output timer output (tmp8) n-ch open-drain output selectable. 5 v tolerant. p613/tip81 toq00 40 p53/sib2/kr3/tiq00/rtp03/ ddo note 1 toq01 37 p50/tiq01/kr0/rtp00 toq02 38 p51/rtp01/kr1/tiq02 toq03 39 output timer output (tmq0) n-ch open-drain output selectable. 5 v tolerant. p52/tiq03/kr2/rtp02/ddi note 1 txda0 25 p30/sob4 txda1 61 p90/a0/kr6/sda02 note 2 txda2 35 p38/sda00 note 2 txda3 60 output serial transmit data output (uarta0 to uarta3) n-ch open-drain output selectable. 5 v tolerant. p81 v dd 9 ? positive power supply pin for internal ? v ss 11 ? ground potential for internal ? wait 85 input external wait input pcm0 wr0 95 write strobe for external memory (lower 8 bits) pct0 wr1 96 output write strove for external memory (higher 8 bits) pct1 x1 12 input ? x2 13 ? connection of resonator for main clock ? xt1 15 input ? xt2 16 ? connection of resonator for subclock ? notes 1. flash memory versions only 2. i 2 c bus versions (y products) only chapter 2 pin functions user?s manual u16603ej5v1ud 49 2.2 pin states the operation states of pins in the various modes are described below. table 2-2. pin operation states in various modes pin name during reset (immediately after power is turned on) during reset (except immediately after power is turned on) halt mode note 2 idle1, idle2, sub-idle mode note 2 stop mode note 2 idle state note 3 bus hold p05/drst note 4 pulled down pulled down note 5 held held held held held p10/ano0, p11/ano1 hi-z held held note 11 held held p53/ddo note 4 undefined note 1 hi-z note 6 held held held held held ad0 to ad15 notes 8, 9 a0 to a15 undefined notes 8, 10 a16 to a23 undefined note 8 hi-z hi-z held hi-z wait ? ? ? ? ? clkout operating l l operating operating wr0, wr1 rd astb h note 8 hi-z hldak h h h l hldrq operating note 8 ? ? ? operating cs0 to cs3 hi-z note 7 hi-z note 7 h note 8 h h held hi-z other port pins hi-z hi-z held held held held held notes 1. these pins may momentarily output an un defined level upon power application. 2. operates while an alternate function is operating. 3. in separate bus mode, the state of the pins in the id le state inserted after the t2 state is shown. in multiplexed bus mode, the state of the pins in the idle state inserted after the t3 state is shown. 4. flash memory versions only 5. pulled down during external reset. during internal reset by the watchdog timer, clock monitor, etc., the state of this pin differs according to the ocdm.ocdm0 bit setting. 6. ddo output is specified in the on-chip debug mode. 7. the bus control pins function alternately as port pins, so they are initialized to the input mode (port mode). 8. operates even in the halt mode, during dma operation. 9. in separate bus mode: hi-z in multiplexed bus mode: undefined 10. in separate bus mode 11. in port mode: held when alternate function is used: hi-z remark hi-z: high impedance held: the state during the immediately preceding external bus cycle is held. l: low-level output h: high-level output ? : input without sampling (not acknowledged) chapter 2 pin functions user?s manual u16603ej5v1ud 50 2.3 pin i/o circuit types, i/o buffer power supplies, and connection of unused pins (1/3) pin alternate function pin no. i/o circuit type recommended connection p00 tip61/top61 6 p01 tip60/top60 7 p02 nmi 17 p03 intp0/adtrg 18 p04 intp1 19 10-d input: independently connect to ev dd or ev ss via a resistor. output: leave open. p05 intp2/drst note 1 20 10-n input: independently connect to ev ss via a resistor. fixing to v dd level is prohibited. output: leave open. internally pull-down after reset by reset pin. p06 intp3 21 10-d input: independently connect to ev dd or ev ss via a resistor. output: leave open. p10, p11 ano0, ano1 3, 4 12-d input: independently connect to av ref1 or av ss via a resistor. output: leave open. p30 txda0/sob4 25 10-g p31 rxda0/intp7/sib4 26 p32 ascka0/sckb4/tip00 27 p33 tip01/top01/ctxd1 note 2 28 p34 tip10/top10/crxd1 note 2 29 p35 tip11/top11 30 10-d p36 ctxd0 note 3 /ietx0 note 4 31 10-g p37 crxd0 note 3 /ierx0 note 4 32 p38 txda2/sda00 note 5 35 p39 rxda2/scl00 note 5 36 p40 sib0/sda01 note 5 22 p41 sob0/scl01 note 5 23 p42 sckb0 24 p50 tiq01/kr0/toq01/rtp00 37 p51 tiq02/kr1/toq02/rtp01 38 p52 tiq03/kr2/toq03/rtp02/ ddi note 1 39 p53 sib2/kr3/tiq00/toq00/ rtp03/ddo note 1 40 p54 sob2/kr4/rtp04/dck note 1 41 p55 sckb2/kr5/rtp05/dms note 1 42 10-d input: independently connect to ev dd or ev ss via a resistor. output: leave open. notes 1. flash memory versions only 2. can controller (2-channel) versions only 3. can controller versions only 4. iebus controller versions only 5. i 2 c bus versions (y products) only chapter 2 pin functions user?s manual u16603ej5v1ud 51 (2/3) pin alternate function pin no. i/o circuit type recommended connection p60 to p65 rtp10 to rtp15 43 to 48 10-g p66 sib5 49 10-d p67 sob5 50 10-g p68 sckb5 51 p69 tip70/top70 52 p610 tip71 53 10-d p611 top71 54 10-g p612 tip80/top80 55 p613 tip81/top81 56 10-d p614, p615 ? 57, 58 10-g input: independently connect to ev dd or ev ss via a resistor. output: leave open. p70 to p715 ani0 to ani15 144 to 129 11-g input: independently connect to av ref0 or av ss via a resistor. output: leave open. p80 rxda3, intp8 59 10-d p81 txda3 60 10-g p90 a0/kr6/tdxa1/sda02 note 61 p91 a1/kr7/rxda1/scl02 note 62 p92 a2/tip41/top41 63 p93 a3/tip40/top40 64 p94 a4/tip31/top31 65 p95 a5/tip30/top30 66 p96 a6/tip21/top21 67 p97 a7/sib1/tip20/top20 68 10-d p98 a8/sob1 69 10-g p99 a9/sckb1 70 p910 a10/sib3 71 10-d p911 a11/sob3 72 10-g p912 a12/sckb3 73 p913 a13/intp4 74 p914 a14/intp5/tip51/top51 75 p915 a15/intp6/tip50/top50 76 10-d input: independently connect to ev dd or ev ss via a resistor. output: leave open. pcd0 to pcd3 ? 77 to 80 pcm0 wait 85 pcm1 clkout 86 pcm2 hldak 87 pcm3 hldrq 88 pcm4, pcm5 ? 89, 90 pcs0 to pcs3 cs0 to cs3 81 to 84 pcs4 to pcs7 ? 91 to 94 5 input: independently connect to bv dd or bv ss via a resistor. output: leave open. note i 2 c bus versions (y products) only chapter 2 pin functions user?s manual u16603ej5v1ud 52 (3/3) pin alternate function pin no. i/o circuit type recommended connection pct0, pct1 wr0, wr1 95, 96 pct2, pct3 ? 97, 98 pct4 rd 99 pct5 ? 100 pct6 astb 101 pct7 ? 102 pdh0 to pdh7 a16 to a23 121 to 128 pdl0 to pdl4 ad0 to ad4 105 to 109 pdl5 ad5/flmd1 note 1 110 pdl6 to pdl15 ad6 to ad15 111 to 120 5 input: independently connect to bv dd or bv ss via a resistor. output: leave open. av ref0 ? 1 ? av ref1 ? 5 ? always connect this pin to the power supply (also in the standby mode). av ss ? 2 ? always connect this pin directly to the ground (also in the standby mode). bv dd ? 104 ? always connect this pin to the power supply (also in the standby mode). bv ss ? 103 ? always connect this pin directly to the ground (also in the standby mode). ev dd ? 34 ? always connect this pin to the power supply (also in the standby mode). ev ss ? 33 ? always connect this pin directly to the ground (also in the standby mode). flmd0 note 1 ? 8 ? directly connect to v ss in a mode other than the flash memory programming mode. ic note 2 ? 8 ? directly connect to v ss . regc ? 10 ? connect regulator output stabilization capacitance (4.7 f). reset ? 14 2 ? v dd ? 9 ? always connect this pin to the power supply (also in the standby mode). v ss ? 11 ? always connect this pin directly to the ground (also in the standby mode). x1 ? 12 ? ? x2 ? 13 ? ? xt1 ? 15 16 connect to v ss . xt2 ? 16 16 leave open. notes 1. flash memory versions only 2. mask rom versions only chapter 2 pin functions user?s manual u16603ej5v1ud 53 figure 2-1. pin i/o circuits type 2 schmitt-triggered input with hysteresis characteristics type 5 in data output disable p-ch in/out in/out ev dd /bv dd ev ss /bv ss n-ch input enable type 11-g type 12-d type 10-d data output disable ev dd ev ss note p-ch in/out n-ch open drain input enable data output disable av ref0 p-ch in/out n-ch p-ch n-ch av ref0 (threshold voltage) comparator input enable + _ av ss av ss data output disable input enable av ref1 p-ch in/out n-ch p-ch n-ch analog output voltage av ss type 10-n data output disable ev dd ev ss p-ch in/out n-ch open drain input enable ocdm0 bit note n-ch type 16 p-ch feedback cut-off xt1 xt2 type 10-g data output disable ev dd ev ss p-ch in/out n-ch open drain input enable note hysteresis characteristics are not available in port mode. chapter 2 pin functions user?s manual u16603ej5v1ud 54 2.4 cautions (1) cautions on power application when the power is turned on, the following pins may momentarily output an undefined level. ? p10/ano0 pin ? p11/ano1 pin ? p53/sib2/kr3/tiq00/toq00/rtp03/ddo note pin note the ddo pin is provided only in the flash memory versions. (2) cautions on flmd0 pin to accurately start the user program operation, fix the flmd0 pin to low level from when the reset status has been released until the oscillation stabilization time elaps es and the firmware operation is completed. for details of firmware operation, see 25.3.5 (2) firmware operation (flash memory version only). user?s manual u16603ej5v1ud 55 chapter 3 cpu function the cpu of the v850es/sj2 and v850e s/sj2-h is based on risc archit ecture and executes almost all instructions with one clock by using a 5-stage pipeline. 3.1 features minimum instruction execution time: v850es/sj2: 50 ns (operating with main clock (f xx ) = 20 mhz) v850es/sj2-h: 31.25 ns (operating with main clock (f xx ) = 32 mhz) 30.5 s (operating with subclock (f xt ) = 32.768 khz) memory space program (physical address) space: 64 mb linear data (logical address) space: 4 gb linear general-purpose registers: 32 bits 32 registers internal 32-bit architecture 5-stage pipeline control multiplication/division instruction saturation operation instruction 32-bit shift instruction: 1 clock load/store instruction with long/short format four types of bit manipulation instructions ? set1 ? clr1 ? not1 ? tst1 chapter 3 cpu function user?s manual u16603ej5v1ud 56 3.2 cpu register set the registers of the v850es/sj2 and v850es/sj2-h can be classified into two types: general-purpose program registers and dedicated system registers. all the registers are 32 bits wide. for details, refer to the v850es architecture user?s manual . r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 (zero register) (assembler-reserved register) (stack pointer (sp)) (global pointer (gp)) (text pointer (tp)) (element pointer (ep)) (link pointer (lp)) pc (program counter) psw (program status word) ecr (interrupt source register) fepc fepsw (nmi status saving register) (nmi status saving register) eipc eipsw (interrupt status saving register) (interrupt status saving register) 31 0 31 0 31 0 ctbp (callt base pointer) dbpc dbpsw (exception/debug trap status saving register) (exception/debug trap status saving register) ctpc ctpsw (callt execution status saving register) (callt execution status saving register) chapter 3 cpu function user?s manual u16603ej5v1ud 57 3.2.1 program register set the program registers include general-p urpose registers and a program counter. (1) general-purpose registers (r0 to r31) thirty-two general-purpose registers, r0 to r31, are av ailable. any of these registers can be used to store a data variable or an address variable. however, r0 and r30 are implicitly used by instructions and care must be exercised when these registers are used. r0 always holds 0 and is used for an operation that uses 0 or addressing of offset 0. r30 is used by the sld and sst instructions as a base pointer when these inst ructions access the memory. r1, r3 to r5, and r31 are implicitly used by the assembler and c compiler. when using these registers, save their contents for protection, and then restore the contents after using the registers. r2 is sometimes used by the real-time os. if the real-time os does not use r2, it can be used as a register for variables. table 3-1. program registers name usage operation r0 zero register always holds 0. r1 assembler-reserved register used as work ing register to create 32-bit immediate data r2 register for address/data variable (if real-time os does not use r2) r3 stack pointer used to create a stack frame when a function is called r4 global pointer used to access a global variable in the data area r5 text pointer used as register that i ndicates the beginning of a text area (area where program codes are located) r6 to r29 register for address/data variable r30 element pointer used as base pointer to access memory r31 link pointer used when t he compiler calls a function pc program counter holds the instruction address during program execution remark for further details on the r1, r3 to r5, and r31 that are used in the assembler and c compiler, refer to the ca850 (c compiler package) assembly language user?s manual . (2) program counter (pc) the program counter holds the instructi on address during program execution. the lower 32 bits of this register are valid. bits 31 to 26 are fixed to 0. a carry from bit 25 to 26 is ignored even if it occurs. bit 0 is fixed to 0. this means that execution cannot branch to an odd address. 31 26 25 1 0 pc fixed to 0 instruction address during program execution 0 default value 00000000h chapter 3 cpu function user?s manual u16603ej5v1ud 58 3.2.2 system register set the system registers control the status of the cpu and hold interrupt information. these registers can be read or written by using system register load/sto re instructions (ldsr and stsr), using the system register numbers listed below. table 3-2. system register numbers operand specification system register number system register name ldsr instruction stsr instruction 0 interrupt status saving register (eipc) note 1 1 interrupt status saving register (eipsw) note 1 2 nmi status saving register (fepc) note 1 3 nmi status saving register (fepsw) note 1 4 interrupt source register (ecr) 5 program status word (psw) 6 to 15 reserved for future function expansion (operation is not guaranteed if these registers are accessed) 16 callt execution status saving register (ctpc) 17 callt execution status saving register (ctpsw) 18 exception/debug trap status saving register (dbpc) note 2 note 2 19 exception/debug trap status saving register (dbpsw) note 2 note 2 20 callt base pointer (ctbp) 21 to 31 reserved for future function expansion (operation is not guaranteed if these registers are accessed) notes 1. because only one set of these registers is availa ble, the contents of these registers must be saved by program if multiple interrupts are enabled. 2. these registers can be accessed only during the interval between the execution of the dbtrap instruction or illegal opcode ex ecution and dbret instruction. caution even if eipc or fepc, or bit 0 of ctpc is set to 1 by the ldsr instruction, bit 0 is ignored when execution is returned to the main routine by the reti instruction after interrupt ser vicing (this is because bit 0 of the pc is fixed to 0). set an even value to eipc, fepc, and ctpc (bit 0 = 0). remark : can be accessed : access prohibited chapter 3 cpu function user?s manual u16603ej5v1ud 59 (1) interrupt status saving registers (eipc and eipsw) eipc and eipsw are used to save the status when an interrupt occurs. if a software exception or a maskable interrupt occurs, th e contents of the program counter (pc) are saved to eipc, and the contents of the program status word ( psw) are saved to eipsw (these contents are saved to the nmi status saving registers (fepc and f epsw) if a non-maskable interrupt occurs). the address of the instruction next to the instruction under execution, except some instructions (see 22.8 periods in which interrupts are not acknowledged by cpu ), is saved to eipc when a software exception or a maskable interrupt occurs. the current contents of the psw are saved to eipsw. because only one set of interrupt status saving registers is available, the contents of these registers must be saved by program when multiple interrupts are enabled. bits 31 to 26 of eipc and bits 31 to 8 of eipsw are reserved for future function expansion (these bits are always fixed to 0). the value of eipc is restored to the pc and the val ue of eipsw to the psw by the reti instruction. 31 0 eipc (contents of saved pc) 0 0 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 eipsw (contents of saved psw) 0 0 default value 000000xxh (x: undefined) 87 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 chapter 3 cpu function user?s manual u16603ej5v1ud 60 (2) nmi status saving registers (fepc and fepsw) fepc and fepsw are used to save the status when a non-maskable interrupt (nmi) occurs. if an nmi occurs, the contents of the program counter (pc) are saved to fepc, and those of the program status word (psw) are saved to fepsw. the address of the instruction next to the one of the instruction under exec ution, except some instructions, is saved to fepc when an nmi occurs. the current contents of t he psw are saved to fepsw. because only one set of nmi status saving registers is avai lable, the contents of thes e registers must be saved by program when multiple interrupts are enabled. bits 31 to 26 of fepc and bits 31 to 8 of fepsw are re served for future function expansion (these bits are always fixed to 0). the value of fepc is restored to the pc and the value of fepsw to the psw by the reti instruction. 31 0 fepc (contents of saved pc) 0 0 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 fepsw (contents of saved psw) 0 0 default value 000000xxh (x: undefined) 87 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (3) interrupt source register (ecr) the interrupt source register (ecr) hol ds the source of an exception or in terrupt if an exception or interrupt occurs. this register holds the exception code of each interrupt source. because this register is a read-only register, data cannot be written to this register using the ldsr instruction. 31 0 ecr fecc eicc default value 00000000h 16 15 bit position bit name meaning 31 to 16 fecc exception code of non-maskable interrupt (nmi) 15 to 0 eicc exception code of exception or maskable interrupt chapter 3 cpu function user?s manual u16603ej5v1ud 61 (4) program status word (psw) the program status word (psw) is a collection of flags that indicate th e status of the program (result of instruction execution) and the status of the cpu. if the contents of a bit of this regi ster are changed by using the ldsr instruction, the new contents are validated immediately after completion of ldsr instructi on execution. however if the id flag is set to 1, interrupt requests will not be acknowledged while the ldsr instruction is being executed. bits 31 to 8 of this register are reserved for future function expansion (these bits are fixed to 0). (1/2) 31 0 psw rfu default value 00000020h 87 np 6 ep 5 id 4 sat 3 cy 2 ov 1 sz bit position flag name meaning 31 to 8 rfu reserved field. fixed to 0. 7 np indicates that a non-maskable interrupt (nmi) is being serviced. this bit is set to 1 when an nmi request is acknowledged, disabling multiple interrupts. 0: nmi is not being serviced. 1: nmi is being serviced. 6 ep indicates that an exception is being proces sed. this bit is set to 1 when an exception occurs. even if this bit is set, interrupt requests are acknowledged. 0: exception is not being processed. 1: exception is being processed. 5 id indicates whether a maskable interrupt can be acknowledged. 0: interrupt enabled 1: interrupt disabled 4 sat note indicates that the result of a saturation operation has overflowed and is saturated. because this is a cumulative flag, it is set to 1 when the result of a saturation operation instruction is saturated, and is not cleared to 0 even if the subsequent operation result is not saturated. use the ldsr instruction to clear this bit. th is flag is neither set to 1 nor cleared to 0 by execution of an arithmetic operation instruction. 0: not saturated 1: saturated 3 cy indicates whether a ca rry or a borrow occurs as a result of an operation. 0: carry or borrow does not occur. 1: carry or borrow occurs. 2 ov note indicates whether an overflow occurs during operation. 0: overflow does not occur. 1: overflow occurs. 1 s note indicates whether the result of an operation is negative. 0: the result is positive or 0. 1: the result is negative. 0 z indicates whether the result of an operation is 0. 0: the result is not 0. 1: the result is 0. remark also read note on the next page. chapter 3 cpu function user?s manual u16603ej5v1ud 62 (2/2) note the result of the operation that has performed satura tion processing is determined by the contents of the ov and s flags. the sat flag is set to 1 only when the ov flag is set to 1 when a saturation operation is performed. flag status status of operation result sat ov s result of operation of saturation processing maximum positive value is exceeded 1 1 0 7fffffffh maximum negative value is exceeded 1 1 1 80000000h positive (maximum value is not exceeded) 0 negative (maximum value is not exceeded) holds value before operation 0 1 operation result itself (5) callt execution status saving registers (ctpc and ctpsw) ctpc and ctpsw are callt execut ion status saving registers. when the callt instruction is execut ed, the contents of the program co unter (pc) are saved to ctpc, and those of the program status wo rd (psw) are saved to ctpsw. the contents saved to ctpc are the address of the inst ruction next to callt. the current contents of t he psw are saved to ctpsw. bits 31 to 26 of ctpc and bits 31 to 8 of ctpsw are reserved for future function expansion (fixed to 0). 31 0 ctpc (saved pc contents) 0 0 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 ctpsw (saved psw contents) 0 0 default value 000000xxh (x: undefined) 87 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 chapter 3 cpu function user?s manual u16603ej5v1ud 63 (6) exception/debug trap status saving registers (dbpc and dbpsw) dbpc and dbpsw are exception/debug trap status registers. if an exception trap or debug trap occurs, the contents of the program counter (pc) are saved to dbpc, and those of the program status word (psw) are saved to dbpsw. the contents to be saved to dbpc are the address of th e instruction next to the one that is being executed when an exception trap or debug trap occurs. the current contents of t he psw are saved to dbpsw. this register can be read or written only during the in terval between the execution of the dbtrap instruction or illegal opcode and dbret instruction execution. bits 31 to 26 of dbpc and bits 31 to 8 of dbpsw are reserved for future function expansion (fixed to 0). the value of dbpc is restored to the pc and the value of dbpsw to the psw by the dbret instruction. 31 0 dbpc (saved pc contents) 0 0 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 31 0 dbpsw (saved psw contents) 0 0 default value 000000xxh (x: undefined) 87 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (7) callt base pointer (ctbp) the callt base pointer (ctbp) is used to specify a tabl e address or generate a target address (bit 0 is fixed to 0). bits 31 to 26 of this register are reserved for future function expansion (fixed to 0). 31 0 ctbp (base address) 0 0 default value 0xxxxxxxh (x: undefined) 26 25 0 0 0 0 0 chapter 3 cpu function user?s manual u16603ej5v1ud 64 3.3 operation modes the v850es/sj2 and v850es/sj2-h have the following operation modes. (1) normal operation mode in this mode, each pin related to the bus interface is set to the port mode after system reset has been released. execution branches to the reset entry address of the intern al rom, and then instruction processing is started. (2) flash memory programming mode in this mode, the internal flash memory can be programmed by using a flash memory programmer. the following products are on-chip flash memory versions of the v850es/sj2 and v850es/sj2-h. ? pd70f3264, 70f3264y, 70f3266, 70f3266y, 70f32 74, 70f3274y, 70f3276, 70f3276y, 70f3284, 70f3284y, 70f3286, 70f3286y, 70f3288, 70f3288y, 70f 3266hy, 70f3276hy, 70f3286hy, 70f3288hy (3) on-chip debug mode the v850es/sj2 and v850es/sj2-h are provided with an on-chip debug function that employs the jtag (joint test action group) communicat ion specifications and that is exec uted via an on-chip debug emulator. the on-chip debug function is provided only in the flash memory versions. for details, see chapter 31 on-chip debug function . 3.3.1 specifying operation mode specify the operation mode by using the flmd0 and flmd1 pins. in the normal mode, input a low level to the flmd0/ic pin after the reset status has been released and before the oscillation stabilization time expires and the firmware operation is completed. in the flash memory programming mode, a high level is in put to the flmd0 pin from the flash memory programmer if a flash memory programmer is connected, but it must be input from an external circuit in the self-programming mode. operation when reset is released flmd0 flmd1 operation mode after reset l normal operation mode h l flash memory programming mode h h setting prohibited remark l: low-level input h: high-level input : don?t care chapter 3 cpu function user?s manual u16603ej5v1ud 65 3.4 address space 3.4.1 cpu address space for instruction addressing, up to a combined total of 16 mb of external memory area and internal rom area, plus an internal ram area, are supported in a linear address space (program space) of up to 64 mb. for operand addressing (data access), up to 4 gb of a linear address spac e (data space) is supported. the 4 gb address space, however, is viewed as 64 images of a 64 mb physical address space. this means that the same 64 mb physical address space is accessed regardless of the value of bits 31 to 26. figure 3-1. image on address space program space internal ram area use-prohibited area use-prohibited area external memory area internal rom area (external memory area) data space image 63 image 1 image 0 peripheral i/o area internal ram area programmable peripheral i/o area or use-prohibited area external memory area internal rom area (external memory area) 16 mb 4 gb 64 mb 64 mb caution only the programmable peripheral i/o area is seen as images of 256 mb each in the 4 gb address space. chapter 3 cpu function user?s manual u16603ej5v1ud 66 3.4.2 wraparound of cpu address space (1) program space of the 32 bits of the pc (program counter), the higher 6 bits are fixed to 0 and only the lower 26 bits are valid. the higher 6 bits ignore a carry or borrow from bit 25 to 26 during branch address calculation. therefore, the highest address of the program space, 03ffffffh, and t he lowest address, 00000000h, are contiguous addresses. that the highest address and the lowest address of the program space are contiguous in this way is called wraparound. caution because the 4 kb area of addresses 03fff000h to 03ffffffh is an on-chip peripheral i/o area, instructions cannot be fetc hed from this area. therefore , do not execute an operation in which the result of a branch addr ess calculation affects this area. program space program space (+) direction ( ? ) direction 00000001h 00000000h 03ffffffh 03fffffeh (2) data space the result of an operand address calculation oper ation that exceeds 32 bits is ignored. therefore, the highest address of the data space, ffffffffh, and the lowest address, 00000000h, are contiguous, and wraparound occurs at the boundary of these addresses. data space data space (+) direction ( ? ) direction 00000001h 00000000h ffffffffh fffffffeh chapter 3 cpu function user?s manual u16603ej5v1ud 67 3.4.3 memory map the areas shown below are reserved in the v850es/sj2 and v850es/sj2-h. figure 3-2. data memory map (physical addresses) (80 kb) use prohibited external memory area (14 mb) internal rom area note 4 (1 mb) external memory area (1 mb) internal ram area (60 kb) on-chip peripheral i/o area (4 kb) use prohibited note 1 (2 mb) 03ffffffh 03fec000h 01000000h 00ffffffh 00200000h 001fffffh 00000000h 03febfffh 03ffffffh 03fff000h 03ffefffh 03ff0000h 03feffffh programmable peripheral i/o area note 2 or use prohibited note 3 03fef000h 03feefffh 03fec000h 001fffffh 00100000h 000fffffh 00000000h notes 1. use of addresses 03fef000h to 03feffffh is pr ohibited because these addresses are in the same area as the on-chip peripheral i/o area. 2. only the programmable peripheral i/o area can be viewed in the 4 gb address space as t he image in 256 mb unit. 3. in the can controller version, addresses 03fec000h to 03fecbffh are assigned as a programmable peripheral i/o area in addre sses 03fec000h to 03feefffh. use of these addresses in a version without a can controller is prohibited. 4. fetch access and read access to addresses 000 00000h to 000fffffh is made to the internal rom area. however, data write access to these addresses is made to the external memory area. chapter 3 cpu function user?s manual u16603ej5v1ud 68 figure 3-3. program memory map internal ram area (60 kb) use prohibited (program fetch prohibited area) use prohibited (program fetch prohibited area) external memory area (14 mb) external memory area (1 mb) internal rom area (1 mb) 03ffffffh 03fff000h 03ffefffh 01000000h 00ffffffh 03ff0000h 03feffffh 00200000h 001fffffh 00100000h 000fffffh 00000000h chapter 3 cpu function user?s manual u16603ej5v1ud 69 3.4.4 areas (1) internal rom area up to 1 mb is reserved as an internal rom area. (a) internal rom (384 kb) 384 kb mask rom or flash memory is allocated to addresses 0000000 0h to 0005ffffh in the following versions. accessing addresses 00060000h to 000fffffh is prohibited. ? pd703264, 703264y, 703274, 703274y, 703284, 703284y, 70f3264, 70f3264y, 70f3274, 70f3274y, 70f3284, 70f3284y figure 3-4. internal rom area (384 kb) access-prohibited area internal rom (384 kb) 00060000h 0005ffffh 00000000h 000fffffh chapter 3 cpu function user?s manual u16603ej5v1ud 70 (b) internal rom (512 kb) 512 kb mask rom is allocated to addresses 00000000h to 0007ffffh in the following versions. accessing addresses 00080000h to 000fffffh is prohibited. ? pd703265, 703265y, 703275, 703275y, 703285, 703285y, 703287, 703287y, 703265hy, 703275hy, 703285hy, 703287hy figure 3-5. internal rom area (512 kb) access-prohibited area internal rom (512 kb) 00080000h 0007ffffh 00000000h 000fffffh (c) internal rom (640 kb) 640 kb mask rom or flash memory is allocated to addresses 0000000 0h to 0009ffffh in the following versions. accessing addresses 000a0000h to 000fffffh is prohibited. ? pd703266, 703266y, 703276, 703276y, 703286, 7 03286y, 703288, 703288y, 70f3266, 70f3266y, 70f3276, 70f3276y, 70f3286, 70f 3286y, 70f3288, 70f3288y, 703266hy, 703276hy, 703286hy, 703288hy, 70f3266hy, 70f3276hy, 70f3286hy, 70f3288hy figure 3-6. internal rom area (640 kb) access-prohibited area internal rom (640 kb) 000a0000h 0009ffffh 00000000h 000fffffh chapter 3 cpu function user?s manual u16603ej5v1ud 71 (2) internal ram area up to 60 kb are reserved as the internal ram area. (a) internal ram (32 kb) 32 kb ram is allocated to addresses 03ff7000h to 03ffefffh of the following versions. accessing addresses 03ff0000h to 03ff6fffh is prohibited. ? pd703264, 703264y, 703274, 703274y, 703284, 703284y, 70f3264, 70f3264y, 70f3274, 70f3274y, 70f3284, 70f3284y figure 3-7. internal ram area (32 kb) access-prohibited area internal ram (32 kb) 03ff7000h 03ff6fffh 03ff0000h 03ffefffh ffff7000h ffff6fffh ffff0000h ffffefffh physical address space logical address space (b) internal ram (40 kb) 40 kb ram is allocated to addresses 03ff5000h to 03ffefffh of the following versions. accessing addresses 03ff0000h to 03ff4fffh is prohibited. ? pd703265, 703265y, 703275, 703275y, 703285, 703285y, 703287, 703287y, 703265hy, 703275hy, 703285hy, 703287hy figure 3-8. internal ram area (40 kb) access-prohibited area internal ram (40 kb) 03ff5000h 03ff4fffh 03ff0000h 03ffefffh ffff5000h ffff4fffh ffff0000h ffffefffh physical address space logical address space chapter 3 cpu function user?s manual u16603ej5v1ud 72 (c) internal ram (48 kb) 48 kb ram is allocated to addresses 03ff3000h to 03ffefffh of the following versions. accessing addresses 03ff0000h to 03ff2fffh is prohibited. ? pd703266, 703266y, 703276, 703276y, 703286, 7 03286y, 703288, 703288y, 70f3266, 70f3266y, 70f3276, 70f3276y, 70f3286, 70f 3286y, 70f3288, 70f3288y, 703266hy, 703276hy, 703286hy, 703288hy, 70f3266hy, 70f3276hy, 70f3286hy, 70f3288hy figure 3-9. internal ram area (48 kb) access-prohibited area internal ram (48 kb) 03ff3000h 03ff2fffh 03ff0000h 03ffefffh physical address space logical address space ffff3000h ffff2fffh ffff0000h ffffefffh chapter 3 cpu function user?s manual u16603ej5v1ud 73 (3) on-chip peripheral i/o area 4 kb of addresses 03fff000h to 03ffffffh are re served as the on-chip peripheral i/o area. figure 3-10. on-chip peripheral i/o area on-chip peripheral i/o area (4 kb) 03ffffffh 03fff000h ffffffffh fffff000h physical address space logical address space peripheral i/o registers that have functions to specif y the operation mode for and mo nitor the status of the on- chip peripheral i/o are mapped to the on-chip periphe ral i/o area. program cannot be fetched from this area. cautions 1. when a register is accessed in word units, a word area is accessed twice in halfword units in the order of lower area and higher area, with the lower 2 bits of the address ignored. 2. if a register that can be accessed in byte units is accessed in halfword units, the higher 8 bits are undefined when the register is read , and data is written to the lower 8 bits. 3. addresses not defined as registers are r eserved for future expansion. the operation is undefined and not guaranteed when these addresses are accessed. 4. the internal rom/ram area and on-chip peripheral i/o area are assigned to successive addresses. when accessing the internal rom/ram area by incrementi ng or decrementing addresses using pointer operations and such, therefore, be careful not to access the on-chip peripheral i/o area by mistakenly extendi ng over the internal rom/ram area boundary. chapter 3 cpu function user?s manual u16603ej5v1ud 74 (4) programmable peripheral i/o area cautions 1. the programmable peripheral i/o area exists only in the can controller versions. this area cannot be used with products that are not equipped with the can controller. 2. only the programmable peripheral i/o area is seen as images of 256 mb each in the 4 gb address space. 12 kb of addresses 03fec000h to 03feefffh are rese rved as the programmable peripheral i/o area. figure 3-11. programmable peripheral i/o area programmable peripheral i/o area (12 kb) 03feefffh 03fec000h (5) external memory area 15 mb (00100000h to 00ffffffh) are allocated as th e external memory area. for details, see chapter 5 bus control function . chapter 3 cpu function user?s manual u16603ej5v1ud 75 3.4.5 recommended use of address space the architecture of the v850es/sj2 a nd v850es/sj2-h requires that a regist er that serves as a pointer be secured for address generation when operand data in the data space is accessed. the address stored in this pointer 32 kb can be directly accessed by an instruction for operand data. because the number of general-purpose registers that can be used as a pointer is limited, however, by keeping the performance from dropping during address calculation when a pointer value is changed, as many gen eral-purpose registers as possible can be secured for variables, and the program size can be reduced. (1) program space of the 32 bits of the pc (program counte r), the higher 6 bits are fixed to 0, and only the lower 26 bits are valid. regarding the program space, therefore, a 64 mb spac e of contiguous addresses starting from 00000000h unconditionally corresponds to the memory map. to use the internal ram area as the prog ram space, access the following addresses. caution if a branch instruction is at the upper limi t of the internal ram ar ea, a prefetch operation (invalid fetch) straddling the on-chip peripheral i/o area does not occur. ram size access address 48 kb 03ff3000h to 03ffefffh 40 kb 03ff5000h to 03ffefffh 32 kb 03ff7000h to 03ffefffh (2) data space with the v850es/sj2 and v850es/sj2-h, it seems that there are sixty-f our 64 mb address spaces on the 4 gb cpu address space. therefore, the least significant bi t (bit 25) of a 26-bit address is sign-extended to 32 bits and allocated as an address. (a) application example of wraparound if r = r0 (zero register) is specified for the ld/st di sp16 [r] instruction, a range of addresses 00000000h 32 kb can be addressed by sign-extended disp16. all the resources, including the internal hardware, can be addressed by one pointer. the zero register (r0) is a register fixed to 0 by har dware, and practically eliminates the need for registers dedicated to pointers. example pd703264y internal rom area on-chip peripheral i/o area internal ram area 3 2 kb 4 kb 28 kb (r = ) 00007fffh 00000000h fffff000h ffffefffh ffffffffh ffff8000h chapter 3 cpu function user?s manual u16603ej5v1ud 76 figure 3-12. recommended memory map data space program space on-chip peripheral i/o on-chip peripheral i/o internal ram internal ram internal rom external memory use prohibited external memory use prohibited note internal ram program space 64 mb internal rom internal rom ffffffffh fffff000h ffffefffh ffff0000h fffeffffh 04000000h 03ffffffh 03fff000h 03ffefffh 03ff3000h 03ff2fffh 03ff0000h 03feffffh 01000000h 00ffffffh 000a0000h 0009ffffh 00100000h 000fffffh 00000000h ffffffffh fffff000h ffffefffh ffff3000h ffff2fffh ffff0000h fffeffffh 00100000h 000fffffh 00000000h use prohibited note in the can controller version, the data space of addresses 03fec0 00h to 03feefffh is assigned as the programmable peripheral i/o area. only the prog rammable peripheral i/o area is seen as images of 256 mb each in the 4 gb address space. remarks 1. indicates the recommended area. 2. this figure is the recommended memory map of the pd703266hy. chapter 3 cpu function user?s manual u16603ej5v1ud 77 3.4.6 peripheral i/o registers (1/13) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff004h port dl register pdl 0000h note 1 fffff004h port dll register pdll 00h note 1 fffff005h port dlh register pdlh 00h note 1 fffff006h port dh register pdh 00h note 1 fffff008h port cs register pcs 00h note 1 fffff00ah port ct register pct 00h note 1 fffff00ch port cm register pcm 00h note 1 fffff00eh port cd register pcd 00h note 1 fffff024h port dl mode register pmdl ffffh fffff024h port dl mode register l pmdll ffh fffff025h port dl mode register h pmdlh ffh fffff026h port dh mode register pmdh ffh fffff028h port cs mode register pmcs ffh fffff02ah port ct mode register pmct ffh fffff02ch port cm mode register pmcm ffh fffff02eh port cd mode register pmcd ffh fffff044h port dl mode control register pmcdl 0000h fffff044h port dl mode control register l pmcdll 00h fffff045h port dl mode control register h pmcdlh 00h fffff046h port dh mode control register pmcdh 00h fffff048h port cs mode control register pmccs 00h fffff04ah port ct mode control register pmcct 00h fffff04ch port cm mode control register pmccm 00h fffff064h peripheral i/o area select control register bpc note 2 0000h fffff066h bus size configuration register bsc 5555h fffff06eh system wait control register vswc 77h fffff080h dma source addres s register 0l dsa0l undefined fffff082h dma source address register 0h dsa0h undefined fffff084h dma destination address register 0l dda0l undefined fffff086h dma destination address register 0h dda0h undefined fffff088h dma source addres s register 1l dsa1l undefined fffff08ah dma source addres s register 1h dsa1h undefined fffff08ch dma destination address register 1l dda1l undefined fffff08eh dma destination address register 1h dda1h undefined fffff090h dma source addres s register 2l dsa2l undefined fffff092h dma source address register 2h dsa2h undefined fffff094h dma destination address register 2l dda2l undefined fffff096h dma destination address register 2h dda2h undefined fffff098h dma source addres s register 3l dsa3l undefined fffff09ah dma source addr ess register 3h dsa3h r/w undefined notes 1. the output latch is 00h or 0000h. when these regist ers are in the input mode, the pin statuses are read. 2. can controller versions only chapter 3 cpu function user?s manual u16603ej5v1ud 78 (2/13) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff09ch dma destination address register 3l dda3l undefined fffff09eh dma destination address register 3h dda3h undefined fffff0c0h dma transfer count register 0 dbc0 undefined fffff0c2h dma transfer count register 1 dbc1 undefined fffff0c4h dma transfer count register 2 dbc2 undefined fffff0c6h dma transfer count register 3 dbc3 undefined fffff0d0h dma addressing control register 0 dadc0 0000h fffff0d2h dma addressing control register 1 dadc1 0000h fffff0d4h dma addressing control register 2 dadc2 0000h fffff0d6h dma addressing control register 3 dadc3 0000h fffff0e0h dma channel control register 0 dchc0 00h fffff0e2h dma channel control register 1 dchc1 00h fffff0e4h dma channel control register 2 dchc2 00h fffff0e6h dma channel control register 3 dchc3 00h fffff100h interrupt mask register 0 imr0 ffffh fffff100h interrupt mask register 0l imr0l ffh fffff101h interrupt mask register 0h imr0h ffh fffff102h interrupt mask register 1 imr1 ffffh fffff102h interrupt mask register 1l imr1l ffh fffff103h interrupt mask register 1h imr1h ffh fffff104h interrupt mask register 2 imr2 ffffh fffff104h interrupt mask register 2l imr2l ffh fffff105h interrupt mask register 2h imr2h ffh fffff106h interrupt mask register 3 imr3 ffffh fffff106h interrupt mask register 3l imr3l ffh fffff107h interrupt mask register 3h imr3h ffh fffff108h interrupt mask register 4 imr4 ffffh fffff108h interrupt mask register 4l imr4l ffh fffff109h interrupt mask register 4h imr4h ffh fffff110h interrupt control register lviic note 47h fffff112h interrupt control register pic0 47h fffff114h interrupt control register pic1 47h fffff116h interrupt control register pic2 47h fffff118h interrupt control register pic3 47h fffff11ah interrupt control register pic4 47h fffff11ch interrupt control register pic5 47h fffff11eh interrupt control register pic6 47h fffff120h interrupt control register pic7 47h fffff122h interrupt control register tq0ovic 47h fffff124h interrupt control register tq0ccic0 47h fffff126h interrupt control register tq0ccic1 47h fffff128h interrupt control register tq0ccic2 r/w 47h note v850es/sj2 versions only chapter 3 cpu function user?s manual u16603ej5v1ud 79 (3/13) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff12ah interrupt control register tq0ccic3 47h fffff12ch interrupt control register tp0ovic 47h fffff12eh interrupt control register tp0ccic0 47h fffff130h interrupt control register tp0ccic1 47h fffff132h interrupt control register tp1ovic 47h fffff134h interrupt control register tp1ccic0 47h fffff136h interrupt control register tp1ccic1 47h fffff138h interrupt control register tp2ovic 47h fffff13ah interrupt control register tp2ccic0 47h fffff13ch interrupt control register tp2ccic1 47h fffff13eh interrupt control register tp3ovic 47h fffff140h interrupt control register tp3ccic0 47h fffff142h interrupt control register tp3ccic1 47h fffff144h interrupt control register tp4ovic 47h fffff146h interrupt control register tp4ccic0 47h fffff148h interrupt control register tp4ccic1 47h fffff14ah interrupt control register tp5ovic 47h fffff14ch interrupt control register tp5ccic0 47h fffff14eh interrupt control register tp5ccic1 47h fffff150h interrupt control register tm0eqic0 47h fffff1 52 h interrupt control register cb0ric/iicic1 note 47h fffff1 54 h interrupt control register cb0tic 47h fffff156h interrupt control register cb1ric 47h fffff158h interrupt control register cb1tic 47h fffff15ah interrupt control register cb2ric 47h fffff15ch interrupt control register cb2tic 47h fffff15eh interrupt control register cb3ric 47h fffff160h interrupt control register cb3tic 47h fffff162h interrupt control register ua0ric/cb4ric 47h fffff164h interrupt control register ua0tic/cb4tic 47h fffff166h interrupt control register ua1ric/iicic2 note 47h fffff168h interrupt control register ua1tic 47h fffff16ah interrupt control register ua2ric/iicic0 note 47h fffff16ch interrupt control register ua2tic 47h fffff16eh interrupt control register adic 47h fffff170h interrupt control register dmaic0 47h fffff172h interrupt control register dmaic1 47h fffff174h interrupt control register dmaic2 47h fffff176h interrupt control register dmaic3 47h fffff178h interrupt control register kric 47h fffff17ah interrupt control register wtiic 47h fffff17ch interrupt control register wtic r/w 47h note i 2 c bus versions (y products) only chapter 3 cpu function user?s manual u16603ej5v1ud 80 (4/13) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff17eh interrupt control register erric0 note 1 / erric note 2 47h fffff180h interrupt control register wupic0 note 1 / staic note 2 47h fffff182h interrupt control register recic0 note 1 / ieic1 note 2 47h fffff184h interrupt control register trxic0 note 1 / ieic2 note 2 47h fffff186h interrupt control register erric1 note 3 47h fffff188h interrupt control register wupic1 note 3 47h fffff18ah interrupt control register recic1 note 3 47h fffff18ch interrupt control register trxic1 note 3 47h fffff18eh interrupt control register pic8 47h fffff190h interrupt control register tp6ovic 47h fffff192h interrupt control register tp6ccic0 47h fffff194h interrupt control register tp6ccic1 47h fffff196h interrupt control register tp7ovic 47h fffff198h interrupt control register tp7ccic0 47h fffff19ah interrupt control register tp7ccic1 47h fffff19ch interrupt control register tp8ovic 47h fffff19eh interrupt control register tp8ccic0 47h fffff1a0h interrupt control register tp8ccic1 47h fffff1a2h interrupt control register cb5ric 47h fffff1a4h interrupt control register cb5tic 47h fffff1a6h interrupt control register ua3ric 47h fffff1a8h interrupt control register ua3tic r/w 47h fffff1fah in-service priority register ispr r 00h fffff1fch command register prcmd w undefined fffff1feh power save control register psc 00h fffff200h a/d converter mode register 0 ada0m0 00h fffff201h a/d converter mode register 1 ada0m1 00h fffff202h a/d converter channel specification register ada0s 00h fffff203h a/d converter mode register 2 ada0m2 00h fffff204h power-fail compare mode register ada0pfm 00h fffff205h power-fail compare threshold value register ada0pft r/w 00h fffff210h a/d conversion result register 0 ada0cr0 undefined fffff211h a/d conversion result register 0h ada0cr0h undefined fffff212h a/d conversion result register 1 ada0cr1 undefined fffff213h a/d conversion result register 1h ada0cr1h undefined fffff214h a/d conversion result register 2 ada0cr2 undefined fffff215h a/d conversion result register 2h ada0cr2h undefined fffff216h a/d conversion result register 3 ada0cr3 undefined fffff217h a/d conversion result register 3h ada0cr3h r undefined notes 1. can controller versions only 2. iebus controller versions only 3. can controller (2-channel) versions only chapter 3 cpu function user?s manual u16603ej5v1ud 81 (5/13) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff218h a/d conversion result register 4 ada0cr4 undefined fffff219h a/d conversion result register 4h ada0cr4h undefined fffff21ah a/d conversion result register 5 ada0cr5 undefined fffff21bh a/d conversion result register 5h ada0cr5h undefined fffff21ch a/d conversion result register 6 ada0cr6 undefined fffff21dh a/d conversion result register 6h ada0cr6h undefined fffff21eh a/d conversion result register 7 ada0cr7 undefined fffff21fh a/d conversion result register 7h ada0cr7h undefined fffff220h a/d conversion result register 8 ada0cr8 undefined fffff221h a/d conversion result register 8h ada0cr8h undefined fffff222h a/d conversion result register 9 ada0cr9 undefined fffff223h a/d conversion result register 9h ada0cr9h undefined fffff224h a/d conversion result register 10 ada0cr10 undefined fffff225h a/d conversion result register 10h ada0cr10h undefined fffff226h a/d conversion result register 11 ada0cr11 undefined fffff227h a/d conversion result register 11h ada0cr11h undefined fffff228h a/d conversion result register 12 ada0cr12 undefined fffff229h a/d conversion result register 12h ada0cr12h undefined fffff22ah a/d conversion result register 13 ada0cr13 undefined fffff22bh a/d conversion result register 13h ada0cr13h undefined fffff22ch a/d conversion result register 14 ada0cr14 undefined fffff22dh a/d conversion result register 14h ada0cr14h undefined fffff22eh a/d conversion result register 15 ada0cr15 undefined fffff22fh a/d conversion result register 15h ada0cr15h undefined fffff280h d/a converter conversion va lue setting register 0 da0cs0 00h fffff281h d/a converter conversion va lue setting register 1 da0cs1 00h fffff282h d/a converter mode register da0m 00h fffff300h key return mode register krm 00h fffff308h selector operation control register 0 selcnt0 00h fffff310h crc input register crcin 00h fffff312h crc data register crcd 0000h fffff318h noise elimination control register nfc 00h fffff320h brg1 prescaler mode register prsm1 00h fffff321h brg1 prescaler compare register prscm1 00h fffff324h brg2 prescaler mode register prsm2 00h fffff325h brg2 prescaler compare register prscm2 00h fffff328h brg3 prescaler mode register prsm3 00h fffff329h brg3 prescaler compare register prscm3 00h fffff340h iic division clock select register ocks0 note 1 00h fffff344h iic division clock select register ocks1 note 1 00h fffff348h iebus clock select register ocks2 note 2 r/w 00h notes 1. i 2 c bus versions (y products) only 2. iebus controller versions only chapter 3 cpu function user?s manual u16603ej5v1ud 82 (6/13) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff360h iebus control register bcr note 1 00h fffff361h iebus power save register psr note 1 r/w 00h fffff362h iebus slave status register ssr note 1 81h fffff363h iebus unit status register usr note 1 r 00h fffff364h iebus interrupt status register isr note 1 00h fffff365h iebus error status register esr note 1 00h fffff366h iebus unit address register uar note 1 0000h fffff368h iebus slave address register sar note 1 r/w 0000h fffff36ah iebus partner address register par note 1 0000h fffff36ch iebus receive slave address register rsa note 1 r 0000h fffff36eh iebus control data register cdr note 1 00h fffff36fh iebus telegraph length register dlr note 1 01h fffff370h iebus data register dr note 1 r/w 00h fffff371h iebus field status register fsr note 1 00h fffff372h iebus success count register scr note 1 01h fffff373h iebus communication count register ccr note 1 r 20h fffff400h port 0 register p0 00h note 2 fffff402h port 1 register p1 00h note 2 fffff406h port 3 register p3 0000h note 2 fffff406h port 3 register l p3l 00h note 2 fffff407h port 3 register h p3h 00h note 2 fffff408h port 4 register p4 00h note 2 fffff40ah port 5 register p5 00h note 2 fffff40ch port 6 register p6 0000h note 2 fffff40ch port 6 register l p6l 00h note 2 fffff40dh port 6 register h p6h 00h note 2 fffff40eh port 7 register l p7l 00h note 2 fffff40fh port 7 register h p7h 00h note 2 fffff410h port 8 register p8 00h note 2 fffff412h port 9 register p9 0000h note 2 fffff412h port 9 register l p9l 00h note 2 fffff413h port 9 register h p9h 00h note 2 fffff420h port 0 mode register pm0 ffh fffff422h port 1 mode register pm1 ffh fffff426h port 3 mode register pm3 ffffh fffff426h port 3 mode register l pm3l ffh fffff427h port 3 mode register h pm3h ffh fffff428h port 4 mode register pm4 ffh fffff42ah port 5 mode register pm5 r/w ffh notes 1. iebus controller versions only 2. the output latch is 00h or 0000h. when these registers are input, the pin statuses are read. chapter 3 cpu function user?s manual u16603ej5v1ud 83 (7/13) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff42ch port 6 mode register pm6 ffffh fffff42ch port 6 mode register l pm6l ffh fffff42dh port 6 mode register h pm6h ffh fffff42eh port 7 mode register l pm7l ffh fffff42fh port 7 mode register h pm7h ffh fffff430h port 8 mode register pm8 ffh fffff432h port 9 mode register pm9 ffffh fffff432h port 9 mode register l pm9l ffh fffff433h port 9 mode register h pm9h ffh fffff440h port 0 mode control register pmc0 00h fffff446h port 3 mode control register pmc3 0000h fffff446h port 3 mode control register l pmc3l 00h fffff447h port 3 mode control register h pmc3h 00h fffff448h port 4 mode control register pmc4 00h fffff44ah port 5 mode control register pmc5 00h fffff44ch port 6 mode control register pmc6 0000h fffff44ch port 6 mode control register l pmc6l 00h fffff44dh port 6 mode control register h pmc6h 00h fffff450h port 8 mode control register pmc8 00h fffff452h port 9 mode control register pmc9 0000h fffff452h port 9 mode control register l pmc9l 00h fffff453h port 9 mode control register h pmc9h 00h fffff460h port 0 function control register pfc0 00h fffff466h port 3 function control register pfc3 0000h fffff466h port 3 function control register l pfc3l 00h fffff467h port 3 function control register h pfc3h 00h fffff468h port 4 function control register pfc4 00h fffff46ah port 5 function control register pfc5 00h fffff46dh port 6 function control register h pfc6h 00h fffff472h port 9 function control register pfc9 0000h fffff472h port 9 function control register l pfc9l 00h fffff473h port 9 function control register h pfc9h 00h fffff484h data wait control register 0 dwc0 7777h fffff488h address wait control register awc ffffh fffff48ah bus cycle control register bcc aaaah fffff540h tmq0 control register 0 tq0ctl0 00h fffff541h tmq0 control register 1 tq0ctl1 00h fffff542h tmq0 i/o control register 0 tq0ioc0 00h fffff543h tmq0 i/o control register 1 tq0ioc1 00h fffff544h tmq0 i/o control register 2 tq0ioc2 00h fffff545h tmq0 option register 0 tq0opt0 00h fffff546h tmq0 capture/compare register 0 tq0ccr0 0000h fffff548h tmq0 capture/compare register 1 tq0ccr1 r/w 0000h chapter 3 cpu function user?s manual u16603ej5v1ud 84 (8/13) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff54ah tmq0 capture/compare register 2 tq0ccr2 0000h fffff54ch tmq0 capture/compare register 3 tq0ccr3 r/w 0000h fffff54eh tmq0 counter read buffer register tq0cnt r 0000h fffff590h tmp0 control register 0 tp0ctl0 00h fffff591h tmp0 control register 1 tp0ctl1 00h fffff592h tmp0 i/o control register 0 tp0ioc0 00h fffff593h tmp0 i/o control register 1 tp0ioc1 00h fffff594h tmp0 i/o control register 2 tp0ioc2 00h fffff595h tmp0 option register 0 tp0opt0 00h fffff596h tmp0 capture/compare register 0 tp0ccr0 0000h fffff598h tmp0 capture/compare register 1 tp0ccr1 r/w 0000h fffff59ah tmp0 counter read buffer register tp0cnt r 0000h fffff5a0h tmp1 control register 0 tp1ctl0 00h fffff5a1h tmp1 control register 1 tp1ctl1 00h fffff5a2h tmp1 i/o control register 0 tp1ioc0 00h fffff5a3h tmp1 i/o control register 1 tp1ioc1 00h fffff5a4h tmp1 i/o control register 2 tp1ioc2 00h fffff5a5h tmp1 option register 0 tp1opt0 00h fffff5a6h tmp1 capture/compare register 0 tp1ccr0 0000h fffff5a8h tmp1 capture/compare register 1 tp1ccr1 r/w 0000h fffff5aah tmp1 counter read buffer register tp1cnt r 0000h fffff5b0h tmp2 control register 0 tp2ctl0 00h fffff5b1h tmp2 control register 1 tp2ctl1 00h fffff5b2h tmp2 i/o control register 0 tp2ioc0 00h fffff5b3h tmp2 i/o control register 1 tp2ioc1 00h fffff5b4h tmp2 i/o control register 2 tp2ioc2 00h fffff5b5h tmp2 option register 0 tp2opt0 00h fffff5b6h tmp2 capture/compare register 0 tp2ccr0 0000h fffff5b8h tmp2 capture/compare register 1 tp2ccr1 r/w 0000h fffff5bah tmp2 counter read buffer register tp2cnt r 0000h fffff5c0h tmp3 control register 0 tp3ctl0 00h fffff5c1h tmp3 control register 1 tp3ctl1 00h fffff5c2h tmp3 i/o control register 0 tp3ioc0 00h fffff5c3h tmp3 i/o control register 1 tp3ioc1 00h fffff5c4h tmp3 i/o control register 2 tp3ioc2 00h fffff5c5h tmp3 option register 0 tp3opt0 00h fffff5c6h tmp3 capture/compare register 0 tp3ccr0 0000h fffff5c8h tmp3 capture/compare register 1 tp3ccr1 r/w 0000h fffff5cah tmp3 counter read buffer register tp3cnt r 0000h fffff5d0h tmp4 control register 0 tp4ctl0 00h fffff5d1h tmp4 control register 1 tp4ctl1 00h fffff5d2h tmp4 i/o control register 0 tp4ioc0 00h fffff5d3h tmp4 i/o control register 1 tp4ioc1 r/w 00h chapter 3 cpu function user?s manual u16603ej5v1ud 85 (9/13) manipulatable bits address function register name symbol r/w 1 8 16 default value fffff5d4h tmp4 i/o control register 2 tp4ioc2 00h fffff5d5h tmp4 option register 0 tp4opt0 00h fffff5d6h tmp4 capture/compare register 0 tp4ccr0 0000h fffff5d8h tmp4 capture/compare register 1 tp4ccr1 r/w 0000h fffff5dah tmp4 counter read buffer register tp4cnt r 0000h fffff5e0h tmp5 control register 0 tp5ctl0 00h fffff5e1h tmp5 control register 1 tp5ctl1 00h fffff5e2h tmp5 i/o control register 0 tp5ioc0 00h fffff5e3h tmp5 i/o control register 1 tp5ioc1 00h fffff5e4h tmp5 i/o control register 2 tp5ioc2 00h fffff5e5h tmp5 option register 0 tp5opt0 00h fffff5e6h tmp5 capture/compare register 0 tp5ccr0 0000h fffff5e8h tmp5 capture/compare register 1 tp5ccr1 r/w 0000h fffff5eah tmp5 counter read buffer register tp5cnt r 0000h fffff5f0h tmp6 control register 0 tp6ctl0 00h fffff5f1h tmp6 control register 1 tp6ctl1 00h fffff5f2h tmp6 i/o control register 0 tp6ioc0 00h fffff5f3h tmp6 i/o control register 1 tp6ioc1 00h fffff5f4h tmp6 i/o control register 2 tp6ioc2 00h fffff5f5h tmp6 option register 0 tp6opt0 00h fffff5f6h tmp6 capture/compare register 0 tp6ccr0 0000h fffff5f8h tmp6 capture/compare register 1 tp6ccr1 r/w 0000h fffff5fah tmp6 counter read buffer register tp6cnt r 0000h fffff600h tmp7 control register 0 tp7ctl0 00h fffff601h tmp7 control register 1 tp7ctl1 00h fffff602h tmp7 i/o control register 0 tp7ioc0 00h fffff603h tmp7 i/o control register 1 tp7ioc1 00h fffff604h tmp7 i/o control register 2 tp7ioc2 00h fffff605h tmp7 option register 0 tp7opt0 00h fffff606h tmp7 capture/compare register 0 tp7ccr0 0000h fffff608h tmp7 capture/compare register 1 tp7ccr1 r/w 0000h fffff60ah tmp7 counter read buffer register tp7cnt r 0000h fffff610h tmp8 control register 0 tp8ctl0 00h fffff611h tmp8 control register 1 tp8ctl1 00h fffff612h tmp8 i/o control register 0 tp8ioc0 00h fffff613h tmp8 i/o control register 1 tp8ioc1 00h fffff614h tmp8 i/o control register 2 tp8ioc2 00h fffff615h tmp8 option register 0 tp8opt0 00h fffff616h tmp8 capture/compare register 0 tp8ccr0 0000h fffff618h tmp8 capture/compare register 1 tp8ccr1 r/w 0000h fffff61ah tmp8 counter read buffer register tp8cnt r 0000h fffff680h watch timer operation mode register wtm 00h fffff690h tmm0 control register 0 tm0ctl0 r/w 00h chapter 3 cpu function user?s manual u16603ej5v1ud 86 (10/13) manipulatable bits address function register name symbol r/w 1 8 16 32 default value fffff694h tmm0 compare register 0 tm0cmp0 0000h fffff6c0h oscillation stabilization time select register osts 06h fffff6c1h pll lockup time specification register plls 03h fffff6d0h watchdog timer mode register 2 wdtm2 67h fffff6d1h watchdog timer enable register wdte 9ah fffff6e0h real-time output buffer register 0l rtbl0 00h fffff6e2h real-time output buffer register 0h rtbh0 00h fffff6e4h real-time output port mode register 0 rtpm0 00h fffff6e5h real-time output port control register 0 rtpc0 00h fffff6f0h real-time output buffer register 1l rtbl1 00h fffff6f2h real-time output buffer register 1h rtbh1 00h fffff6f4h real-time output port mode register 1 rtpm1 00h fffff6f5h real-time output port control register 1 rtpc1 00h fffff706h port 3 function control expansion register l pfce3l 00h fffff70ah port 5 function control expansion register pfce5 00h fffff712h port 9 function control expansion register pfce9 0000h fffff712h port 9 function control expansion register l pfce9l 00h fffff713h port 9 function control expansion register h pfce9h 00h fffff802h system status register sys 00h fffff80ch internal oscillation mode register rcm 00h fffff810h dma trigger factor register 0 dtfr0 00h fffff812h dma trigger factor register 1 dtfr1 00h fffff814h dma trigger factor register 2 dtfr2 00h fffff816h dma trigger factor register 3 dtfr3 00h fffff820h power save mode register psmr 00h fffff822h clock control register ckc r/w 0ah fffff824h lock register lockr r 00h fffff828h processor clock control register pcc 03h fffff82ch pll control register pllctl r/w 01h fffff82eh cpu operation clock status register ccls r 00h fffff840h correction address register 0 corad0 00000000h fffff840h correction address register 0l corad0l 0000h fffff842h correction address register 0h corad0h 0000h fffff844h correction address register 1 corad1 00000000h fffff844h correction address register 1l corad1l 0000h fffff846h correction address register 1h corad1h 0000h fffff848h correction address register 2 corad2 00000000h fffff848h correction address register 2l corad2l 0000h fffff84ah correction address register 2h corad2h 0000h fffff84ch correction address register 3 corad3 00000000h fffff84ch correction address register 3l corad3l 0000h fffff84eh correction address register 3h corad3h 0000h fffff870h clock monitor mode register clm r/w 00h chapter 3 cpu function user?s manual u16603ej5v1ud 87 (11/13) manipulatable bits address function register name symbol r/w 1 8 16 32 default value fffff880h correction control register corcn 00h fffff888h reset source flag register resf 00h fffff890h low voltage detection register lvim note 1 00h fffff891h low voltage detection level select register lvis note 1 00h fffff892h internal ram data status register rams 01h fffff8b0h prescaler mode register 0 prsm0 00h fffff8b1h prescaler compare register 0 prscm0 00h fffff9fch on-chip debug mode register ocdm 01h fffff9feh peripheral emul ation register 1 pemu1 note 2 00h fffffa00h uarta0 control register 0 ua0ctl0 10h fffffa01h uarta0 control register 1 ua0ctl1 00h fffffa02h uarta0 control register 2 ua0ctl2 ffh fffffa03h uarta0 option control register 0 ua0opt0 14h fffffa04h uarta0 status register ua0str r/w 00h fffffa06h uarta0 receive data register ua0rx r ffh fffffa07h uarta0 transmit data register ua0tx ffh fffffa10h uarta1 control register 0 ua1ctl0 10h fffffa11h uarta1 control register 1 ua1ctl1 00h fffffa12h uarta1 control register 2 ua1ctl2 ffh fffffa13h uarta1 option control register 0 ua1opt0 14h fffffa14h uarta1 status register ua1str r/w 00h fffffa16h uarta1 receive data register ua1rx r ffh fffffa17h uarta1 transmit data register ua1tx ffh fffffa20h uarta2 control register 0 ua2ctl0 10h fffffa21h uarta2 control register 1 ua2ctl1 00h fffffa22h uarta2 control register 2 ua2ctl2 ffh fffffa23h uarta2 option control register 0 ua2opt0 14h fffffa24h uarta2 status register ua2str r/w 00h fffffa26h uarta2 receive data register ua2rx r ffh fffffa27h uarta2 transmit data register ua2tx ffh fffffa30h uarta3 control register 0 ua3ctl0 10h fffffa31h uarta3 control register 1 ua3ctl1 00h fffffa32h uarta3 control register 2 ua3ctl2 ffh fffffa33h uarta3 option control register 0 ua3opt0 14h fffffa34h uarta3 status register ua3str r/w 00h fffffa36h uarta3 receive data register ua3rx r ffh fffffa37h uarta3 transmit data register ua3tx ffh fffffc00h external interrupt falling edge specification register 0 intf0 00h fffffc06h external interrupt falling edge specification register 3 intf3 00h fffffc10h external interrupt falling edge specification register 8 intf8 00h fffffc13h external interrupt falling edge specification register 9h intf9h r/w 00h notes 1. v850es/sj2 only 2. only during emulation chapter 3 cpu function user?s manual u16603ej5v1ud 88 (12/13) manipulatable bits address function register name symbol r/w 1 8 16 default value fffffc20h external interrupt rising edge specification register 0 intr0 00h fffffc26h external interrupt rising edge specification register 3 intr3 00h fffffc30h external interrupt rising edge specification register 8 intr8 00h fffffc33h external interrupt rising edge specification register 9h intr9h 00h fffffc60h port 0 function register pf0 00h fffffc66h port 3 function register pf3 0000h fffffc66h port 3 function register l pf3l 00h fffffc67h port 3 function register h pf3h 00h fffffc68h port 4 function register pf4 00h fffffc6ah port 5 function register pf5 00h fffffc6ch port 6 function register pf6 0000h fffffc6ch port 6 function register l pf6l 00h fffffc6dh port 6 function register h pf6h 00h fffffc70h port 8 function register pf8 00h fffffc72h port 9 function register pf9 0000h fffffc72h port 9 function register l pf9l 00h fffffc73h port function 9 control register h pf9h 00h fffffd00h csib0 control register 0 cb0ctl0 01h fffffd01h csib0 control register 1 cb0ctl1 00h fffffd02h csib0 control register 2 cb0ctl2 00h fffffd03h csib0 status register cb0str r/w 00h fffffd04h csib0 receive data register cb0rx 0000h fffffd04h csib0 receive data register l cb0rxl r 00h fffffd06h csib0 transmit data register cb0tx 0000h fffffd06h csib0 transmit data register l cb0txl 00h fffffd10h csib1 control register 0 cb1ctl0 01h fffffd11h csib1 control register 1 cb1ctl1 00h fffffd12h csib1 control register 2 cb1ctl2 00h fffffd13h csib1 status register cb1str r/w 00h fffffd14h csib1 receive data register cb1rx 0000h fffffd14h csib1 receive data register l cb1rxl r 00h fffffd16h csib1 transmit data register cb1tx 0000h fffffd16h csib1 transmit data register l cb1txl 00h fffffd20h csib2 control register 0 cb2ctl0 01h fffffd21h csib2 control register 1 cb2ctl1 00h fffffd22h csib2 control register 2 cb2ctl2 00h fffffd23h csib2 status register cb2str r/w 00h fffffd24h csib2 receive data register cb2rx 0000h fffffd24h csib2 receive data register l cb2rxl r 00h fffffd26h csib2 transmit data register cb2tx 0000h fffffd26h csib2 transmit data register l cb2txl 00h fffffd30h csib3 control register 0 cb3ctl0 01h fffffd31h csib3 control register 1 cb3ctl1 r/w 00h chapter 3 cpu function user?s manual u16603ej5v1ud 89 (13/13) manipulatable bits address function register name symbol r/w 1 8 16 default value fffffd32h csib3 control register 2 cb3ctl2 00h fffffd33h csib3 status register cb3str r/w 00h fffffd34h csib3 receive data register cb3rx 0000h fffffd34h csib3 receive data register l cb3rxl r 00h fffffd36h csib3 transmit data register cb3tx 0000h fffffd36h csib3 transmit data register l cb3txl 00h fffffd40h csib4 control register 0 cb4ctl0 01h fffffd41h csib4 control register 1 cb4ctl1 00h fffffd42h csib4 control register 2 cb4ctl2 00h fffffd43h csib4 status register cb4str r/w 00h fffffd44h csib4 receive data register cb4rx 0000h fffffd44h csib4 receive data register l cb4rxl r 00h fffffd46h csib4 transmit data register cb4tx 0000h fffffd46h csib4 transmit data register l cb4txl 00h fffffd50h csib5 control register 0 cb5ctl0 01h fffffd51h csib5 control register 1 cb5ctl1 00h fffffd52h csib5 control register 2 cb5ctl2 00h fffffd53h csib5 status register cb5str r/w 00h fffffd54h csib5 receive data register cb5rx 0000h fffffd54h csib5 receive data register l cb5rxl r 00h fffffd56h csib5 transmit data register cb5tx 0000h fffffd56h csib5 transmit data register l cb5txl 00h fffffd80h iic shift register 0 note iic0 00h fffffd82h iic control register 0 note iicc0 00h fffffd83h slave address register 0 note sva0 00h fffffd84h iic clock select register 0 note iiccl0 00h fffffd85h iic function expansion register 0 note iicx0 r/w 00h fffffd86h iic status register 0 note iics0 r 00h fffffd8ah iic flag register 0 note iicf0 00h fffffd90h iic shift register 1 note iic1 00h fffffd92h iic control register 1 note iicc1 00h fffffd93h slave address register 1 note sva1 00h fffffd94h iic clock select register 1 note iiccl1 00h fffffd95h iic function expansion register 1 note iicx1 r/w 00h fffffd96h iic status register 1 note iics1 r 00h fffffd9ah iic flag register 1 note iicf1 00h fffffda0h iic shift register 2 note iic2 00h fffffda2h iic control register 2 note iicc2 00h fffffda3h slave address register 2 note sva2 00h fffffda4h iic clock select register 2 note iiccl2 00h fffffda5h iic function expansion register 2 note iicx2 r/w 00h fffffda6h iic status register 2 note iics2 r 00h fffffdaah iic flag register 2 note iicf2 00h ffffffbeh external bus interface mode control register eximc r/w 00h note i 2 c bus versions (y products) only chapter 3 cpu function user?s manual u16603ej5v1ud 90 3.4.7 programmable peripheral i/o registers the bpc register is used for programmable peripheral i/o register area selection. (1) peripheral i/o area selec t control register (bpc) the bpc register can be read or written in 16-bit units. reset sets this register to 0000h. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 address default value bpc pa15 0 pa13 pa12 pa11 pa10 pa09 pa08 pa07 pa06 pa05 pa04 pa03 pa02 pa01 pa00 fffff064h 0000h bit position bit name function enables/disables usage of prog rammable peripheral i/o area. pa15 usage of programmable peripheral i/o area 0 usage of programmable peripheral i/o area disabled 1 usage of programmable peripheral i/o area enabled 15 pa15 13 to 0 pa13 to pa00 specify an address in programmabl e peripheral i/o area (corresponding to a27 to a14, respectively). caution when setting the pa15 bit to 1, be sure to set the bpc register to 8ffbh. when clearing the pa15 bit to 0, be su re to set the bpc register to 0000h. for a list of the programmable peripheral i/o register areas, see table 19-16 register access types . 3.4.8 special registers special registers are registers that are protected from being written with illegal data due to a program hang-up. the v850es/sj2 and v850es/sj2-h have eight and seven special registers, respectively. ? power save control register (psc) ? clock control register (ckc) ? processor clock control register (pcc) ? clock monitor mode register (clm) ? reset source flag register (resf) ? low voltage detection register (lvim) note ? internal ram data status register (rams) ? on-chip debug mode register (ocdm) note v850es/sj2 only in addition, the prcdm register is provided to protect again st a write access to the spec ial registers so that the application system does not inadvertently stop due to a program loop. a write access to the special registers is made in a specific sequence, and an illegal store operation is reported to the sys register. chapter 3 cpu function user?s manual u16603ej5v1ud 91 (1) setting data to special registers set data to the special registers in the following sequence. <1> disable dma operation. <2> prepare data to be set to the special register in a general-purpose register. <3> write the data prepared in <2> to the prcmd register. <4> write the setting data to the special re gister (by using the following instructions). ? store instruction (st/sst instruction) ? bit manipulation instruction (set1/clr1/not1 instruction) (<5> to <9> insert nop instructions (5 instructions).) note <10> enable dma operation if necessary. [example] with psc register (setting standby mode) st.b r11, psmr[r0] ; set psmr register (setting idle1, idle2, and stop modes). <1>clr1 0, dchcn[r0] ; disable dma operation. n = 0 to 3 <2>mov0x02, r10 <3>st.b r10, prcmd[r0] ; write prcmd register. <4>st.b r10, psc[r0] ; set psc register. <5>nop note ; dummy instruction <6>nop note ; dummy instruction <7>nop note ; dummy instruction <8>nop note ; dummy instruction <9>nop note ; dummy instruction <10>set1 0, dchcn[r0] ; enable dma operation. n = 0 to 3 (next instruction) there is no special sequence to read a special register. note five nop instructions or more must be inserted immediately after setting the idle1 mode, idle2 mode, or stop mode (by setting the psc.stp bit to 1). cautions 1. when a store instruction is executed to store data in the command register, interrupts are not acknowledged. this is because it is assumed that steps <3> and <4> above are performed by successive store instructions. if another instruction is placed between <3> and <4>, and if an interrupt is acknowledged by that instruction, the above sequence may not be established, causing malfunction. 2. although dummy data is written to th e prcmd register, use the same general-purpose register used to set the speci al register (<4> in example) to write data to the prcmd register (<3> in example). the same applies when a general-purpose register is used for addressing. chapter 3 cpu function user?s manual u16603ej5v1ud 92 (2) command register (prcmd) the prcmd register is an 8-bit regist er that protects the registers that may seriously affect the application system from being written, so that the system does not inadvertently stop due to a program hang-up. the first write access to a special register is valid after data has be en written in advance to the prcmd register. in this way, the value of the special register can be rewritten only in a specific sequence, so as to protect the register from an illegal write access. the prcmd register is write-only, in 8-bit units (undefined data is read when this register is read). 7 reg7 prcmd 6 reg6 5 reg5 4 reg4 3 reg3 2 reg2 1 reg1 0 reg0 after reset: undefined w address: fffff1fch chapter 3 cpu function user?s manual u16603ej5v1ud 93 (3) system status register (sys) status flags that indicate the ope ration status of the overall system are allocated to this register. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 protection error did not occur protection error occurred prerr 0 1 detects protection error sys 0 0 0 0 0 0 prerr after reset: 00h r/w address: fffff802h < > the prerr flag operates under the following conditions. (a) set condition (prerr flag = 1) (i) when data is written to a special register without writing anything to the prcmd register (when <4> is executed without executing <3> in 3.4.8 (1) setting data to special registers ) (ii) when data is written to an on-chip peripheral i/o register other than a special register (including execution of a bit manipulation instruction) afte r writing data to the prcmd register (if <4> in 3.4.8 (1) setting data to special registers is not the setting of a special register) remark even if an on-chip peripheral i/o register is read (except by a bit manipulation instruction) between an operation to write the prcmd register and an operation to write a special register, the prerr flag is not set, and the set dat a can be written to the special register. (b) clear condition (prerr flag = 0) (i) when 0 is written to the prerr flag (ii) when the system is reset cautions 1. if 0 is written to the prerr bit of the sys register, which is not a special register, immediately after a write access to the prcm d register, the prerr bit is cleared to 0 (the write access takes precedence). 2. if data is written to the prcmd regist er, which is not a special register, immediately after a write access to the prcmd regi ster, the prerr bit is set to 1. chapter 3 cpu function user?s manual u16603ej5v1ud 94 3.4.9 cautions (1) registers to be set first be sure to set the following registers firs t when using the v850es/sj2 and v850es/sj2-h. ? system wait control register (vswc) ? on-chip debug mode register (ocdm) ? watchdog timer mode register 2 (wdtm2) after setting the vswc, ocdm, and wdtm2 registers, set the other registers as necessary. when using the external bus, set each pin to the alternate-function bus control pin mode by using the port- related registers after setting the above registers. (a) system wait control register (vswc) the vswc register controls wait of bus a ccess to the on-chip peripheral i/o registers. three clocks are required to access an on-chip per ipheral i/o register (without a wait cycle). the v850es/sj2 and v850es/sj2-h require wait cycles ac cording to the operating frequency. set the following value to the vswc register in accordance with the frequency used. however, if f clk is greater than 20 mhz, only the v 850es/sj2-h can be used. the vswc register can be read or written in 8-bit units (address: fffff06eh, default value: 77h). operating frequency (f clk ) set value of vswc number of waits 32 khz f clk < 16.6 mhz 00h 0 (no waits) 16.6 mhz f clk < 25 mhz 01h 1 25 mhz f clk 32 mhz 11h 2 (b) on-chip debug mode register (ocdm) for details, see chapter 31 on-chip debug function . (c) watchdog timer mode register 2 (wdtm2) the wdtm2 register sets the overflow time and the operation clock of the watchdog timer 2. the watchdog timer 2 automatically st arts in the reset mode after reset is released. write the wdtm2 register to activate this operation. for details, see chapter 11 functions of watchdog timer 2 . chapter 3 cpu function user?s manual u16603ej5v1ud 95 (2) accessing specific on-chip peripheral i/o registers this product has two types of internal system buses. one is a cpu bus and the other is a peripheral bus t hat interfaces with low-speed peripheral hardware. the clock of the cpu bus and the cloc k of the peripheral bus are asynchronous. if an access to the cpu and an access to the peripheral hardware conflict, therefore, unexpected illegal data may be transferred. if there is a possibility of a conflict, the number of cycles for acce ssing the cpu changes when t he peripheral hardware is accessed, so that correct data is transferred. as a re sult, the cpu does not start processing of the next instruction but enters the wait status. if this wait status occurs, the number of clocks required to execute an instruction increases by the number of wait clocks shown below. this must be taken into consideration if real-time processing is required. when specific on-chip peripheral i/o r egisters are accessed, more wait stat es may be required in addition to the wait states set by the vswc register. the access conditions and how to calculate the number of wait states to be inserted (number of cpu clocks) at this time are shown below. (1/2) peripheral function register name access k tpncnt read 1 or 2 read 1 or 2 16-bit timer/event counter p (tmp) (n = 0 to 8) tpnccr0, tpnccr1 write ? 1st access: no wait ? continuous write: 3 or 4 tq0cnt read 1 or 2 read 1 or 2 16-bit timer/event counter q (tmq) tq0ccr0 to tq0ccr3 write ? 1st access: no wait ? continuous write: 3 or 4 watchdog timer 2 (wdt2) wdtm2 write (when wdt2 operating) 3 rtbl0, rtbl1 write (rtpcn.rtpoen bit = 0) 1 real-time output function (rto) rtbh0, rtbh1 write (rtpcn.rtpoen bit = 0) 1 ada0m0 read 1 or 2 ada0cr0 to ada0cr15 read 1 or 2 a/d converter ada0cr0h to ada0cr15h read 1 or 2 i 2 c00 to i 2 c02 note 1 iics0 to iics2 read 1 can controller note 2 (n = 0, 1, m = 0 to 31, a = 1 to 4) cngmabt, cngmabtd, cnmaskal, cnmaskah, cnlec, cninfo, cnerc, cnie, cnints, cnbrp, cnbtr, cnts read/write (f xx /f canmod + 1)/(2 + j) (min.) note 3 (2 f xx /f canmod + 1)/(2 + j) (max.) note 3 chapter 3 cpu function user?s manual u16603ej5v1ud 96 (2/2) peripheral function register name access k cngmctrl, cngmcs, cnctrl read/write (f xx /f can + 1)/(2 + j) (min.) note 3 (2 f xx /f can + 1)/(2 + j) (max.) note 3 write (f xx /f canmod + 1)/(2 + j) (min.) note 3 (2 f xx /f canmod + 1)/(2 + j) (max.) note 3 cnrgpt, cntgpt read (3 f xx /f canmode + 1)/(2 + j) (min.) note 3 (4 f xx /f canmode + 1)/(2 + j) (max.) note 3 cnlipt, cnlopt read (3 f xx /f canmode + 1)/(2 + j) (min.) note (4 f xx /f canmode + 1)/(2 + j) (max.) note 3 write (4 f xx /f can + 1)/(2 + j) (min.) note 3 (5 f xx /f can + 1)/(2 + j) (max.) note 3 cnmctrlm read (3 f xx /f can + 1)/(2 + j) (min.) note 3 (4 f xx /f can + 1)/(2 + j) (max.) note 3 write (8 bits) (4 f xx /f canmode + 1)/(2 + j) (min.) note 3 (5 f xx /f canmode + 1)/(2 + j) (max.) note 3 write (16 bits) (2 f xx /f canmode + 1)/(2 + j) (min.) note 3 (3 f xx /f canmode + 1)/(2 + j) (max.) note 3 can controller note 2 (n = 0, 1, m = 0 to 31, a = 1 to 4) cnmdata01m, cnmdata0m, cnmdata1m, cnmdata23m, cnmdata2m, cnmdata3m, cnmdata45m, cnmdata4m, cnmdata5m, cnmdata67m, cnmdata6m, cnmdata7m, cnmdlcm, cnmconfm, cnmidlm, cnmidhm read (8/16 bits) (3 f xx /f canmode + 1)/(2 + j) (min.) note 3 (4 f xx /f canmode + 1)/(2 + j) (max.) note 3 crc crcd write 1 number of clocks necessary for access = 3 + i + j + (2 + j) k notes 1. i 2 c bus versions (y products) only 2. can controller versions only 3. digits below the decimal point are rounded up. caution accessing the above registers is prohibited in the following statuses. if a wait cycle is generated, it can only be cleared by a reset. ? when the cpu operates with the subclock a nd the main clock oscillation is stopped ? when the cpu operates with th e internal oscillation clock remark f xx : main clock frequency = f xx f canmod : can module system clock f can : supply clock to can i: values (0 or 1) of higher 4 bits of vswc register j: values (0 or 1) of lower 4 bits of vswc register chapter 3 cpu function user?s manual u16603ej5v1ud 97 (3) system reserved area in the flash memory version of the v850es/sj2 and v850es/sj2-h, 0000007ah to 0000007fh is a system reserved area for function expansion, and therefore it is recommended that this area not be used. however, in the case of the special version of the following products, be sure to set 00h to 0000007ah. ? pd70f3264, 70f3264y, 70f3274, 70f32 74y, 70f3284, 70f3284y: ver. 1.0 ? pd70f3266, 70f3266y, 70f3276, 70f 3276y, 70f3286, 70f3286y, 70f3288, 70f3288y: ver. 1.x (x: don?t care) ? pd70f3266hy, 70f3276hy, 70f3286hy, 70f3288hy: no applicable versions remarks 1. with products other than the above (including al l the products listed in this manual), operations are not affected even if 00h is set to 0000007ah. 2. check the product version by the number that follows ds, es, or cs on the third line of the package stamp. if the generic name is stamped (v 850es/sj2, v850es/sj2-h, etc.), the above restriction does not apply. for enquiries, contact an nec electronics sales representative. 0000007ah 0000007bh 0000007fh 00000080h 00000079h 00000070h 00000000h system reserved area (00h) system reserved area security id note (10 bytes) note for the security id, see 31.6.1 security id . caution when the data in the flash memory has been deleted, all the bits are set to 1. chapter 3 cpu function user?s manual u16603ej5v1ud 98 (4) restriction on conflict between sld instruction and interrupt request (a) description if a conflict occurs between the decode operation of an instruction in <2> immediately before the sld instruction following an instruction in <1> and an in terrupt request before the instruction in <1> is complete, the execution result of the instru ction in <1> may not be stored in a register. instruction <1> ? ld instruction: ld.b, ld.h, ld.w, ld.bu, ld.hu ? sld instruction: sld.b, sl d.h, sld.w, sld.bu, sld.hu ? multiplication instruction: mul, mulh, mulhi, mulu instruction <2> mov reg1, reg2 satadd reg1, reg2 and reg1, reg2 add reg1, reg2 mulh reg1, reg2 not reg1, reg2 satadd imm5, reg2 tst reg1, reg2 add imm5, reg2 shr imm5, reg2 satsubr reg1, reg2 or reg1, reg2 subr reg1, reg2 cmp reg1, reg2 sar imm5, reg2 satsub reg1, reg2 xor reg1, reg2 sub reg1, reg2 cmp imm5, reg2 shl imm5, reg2 user?s manual u16603ej5v1ud 99 chapter 4 port functions 4.1 features { i/o ports: 128 ? 5 v tolerant/n-ch open-drain output selectable: 60 (ports 0, 3 to 6, 8, 9) { input/output specifiable in 1-bit units 4.2 basic port configuration the v850es/sj2 and v8 50es/sj2-h feature a total of 128 i/o ports cons isting of ports 0, 1, 3 to 9, cd, cm, cs, ct, dh, and dl. the port configuration is shown below. figure 4-1. port configuration diagram p00 p06 port 0 pcd0 pcd3 port cd pcm0 pcm5 port cm pcs0 pcs7 pct0 pct7 port cs port ct p90 p915 port 9 pdh0 pdh7 port dh pdl0 pdl15 port dl p30 p39 port 3 port 1 p40 p42 port 4 p50 p55 port 5 p60 p615 p70 p715 p80 p81 port 6 p10 p11 port 7 port 8 caution ports 0, 3 to 6, 8, and 9 are 5 v tolerant. table 4-1. i/o buffer power supplies for pins power supply corresponding pins av ref0 port 7 av ref1 port 1 bv dd ports cd, cm, cs, ct, dh, dl ev dd reset, ports 0, 3 to 6, 8, 9 chapter 4 port functions user?s manual u16603ej5v1ud 100 4.3 port configuration table 4-2. port configuration item configuration control register port n mode register (pmn: n = 0, 1, 3 to 9, cd, cm, cs, ct, dh, dl) port n mode control register (pmcn: n = 0, 3 to 6, 8, 9, cm, cs, ct, dh, dl) port n function control register (pfcn: n = 0, 3 to 6, 9) port n function control expansion register (pfcen: n = 3, 5, 9) port n function register (pfn: n = 0, 3 to 6, 8, 9) ports i/o: 128 (1) port n register (pn) data is input from or output to an external device by writing or reading the pn register. the pn register consists of a port latch that holds output data, and a circ uit that reads the status of pins. each bit of the pn register corresponds to one pin of port n, and can be read or written in 1-bit units. pn7 output 0. output 1. pnm 0 1 control of output data (in output mode) pn6 pn5 pn4 pn3 pn2 pn1 pn0 0 1 2 3 7 5 6 7 pn after reset: 00h (output latch) r/w data is written to or read from the pn register as follows, regardless of the setting of the pmcn register. table 4-3. writing/reading pn register setting of pmn register writing to pn register reading from pn register output mode (pmnm = 0) data is written to the output latch note . in the port mode (pmcn = 0), the contents of the output latch are output from the pins. the value of the output latch is read. input mode (pmnm = 1) data is written to the output latch. the pin status is not affected note . the pin status is read. note the value written to the output latch is retained until a new value is written to the output latch. chapter 4 port functions user?s manual u16603ej5v1ud 101 (2) port n mode register (pmn) the pmn register specifies the input or output mode of the corresponding port pin. each bit of this register corresponds to one pin of port n, and the input or output mode can be specified in 1-bit units. pmn7 output mode input mode pmnm 0 1 control of input/output mode pmn6 pmn5 pmn4 pmn3 pmn2 pmn1 pmn0 pmn after reset: ffh r/w (3) port n mode control register (pmcn) the pmcn register specifies the port mode or alternate function. each bit of this register corresponds to one pin of port n, and the mode of the port can be specified in 1-bit units. port mode alternate function mode pmcnm 0 1 specification of operation mode pmcn7 pmcn6 pmcn5 pmcn4 pmcn3 pmcn2 pmcn1 pmcn0 pmcn after reset: 00h r/w (4) port n function control register (pfcn) the pfcn register specifies the alternat e function of a port pin to be used if the pin has two alternate functions. each bit of this register corresponds to one pin of port n, and the alternate function of a port pin can be specified in 1-bit units. pfcn7 pfcn6 pfcn5 pfcn4 pfcn3 pfcn2 pfcn1 pfcn0 pfcn after reset: 00h r/w alternate function 1 alternate function 2 pfcnm 0 1 specification of alternate function chapter 4 port functions user?s manual u16603ej5v1ud 102 (5) port n function control expansion register (pfcen) the pfcen register specifies the alte rnate function of a port pin to be used if the pin has three or more alternate functions. each bit of this register corresponds to one pin of port n, and the alternate function of a port pin can be specified in 1-bit units. pfcn7 pfcn6 pfcn5 pfcn4 pfcn3 pfcn2 pfcn1 pfcn0 pfcen7 pfcen6 pfcen5 pfcen4 pfcen3 pfcen2 pfcen1 pfcen0 after reset: 00h r/w pfcen pfcn alternate function 1 alternate function 2 alternate function 3 alternate function 4 pfcenm 0 0 1 1 specification of alternate function pfcnm 0 1 0 1 (6) port n function register (pfn) the pfn register specifies normal output or n-ch open-drain output. each bit of this register corresponds to one pin of por t n, and the output mode of the port pin can be specified in 1-bit units. pfn7 pfn6 pfn5 pfn4 pfn3 pfn2 pfn1 pfn0 normal output (cmos output) n-ch open-drain output pfnm note 0 1 control of normal output/n-ch open-drain output pfn after reset: 00h r/w note the pfnm bit of the pfn register is valid only when the pmnm bit of the pmn register is 0 (when the output mode is specified) in port mode (pmcnm bit = 0). when the pmnm bit is 1 (when the input mode is specified), the set value of the pfn register is invalid. chapter 4 port functions user?s manual u16603ej5v1ud 103 (7) port setting set a port as illustrated below. figure 4-2. setting of each register and pin function pmcn register output mode input mode pmn register ?0? ?1? ?0? ?1? ?0? ?1? (a) (b) (c) (d) alternate function (when two alternate functions are available) port mode alternate function 1 alternate function 2 pfcn register alternate function (when three or more alternate functions are available) alternate function 1 alternate function 2 alternate function 3 alternate function 4 pfcn register pfcen register pfcenm 0 1 0 1 0 0 1 1 (a) (b) (c) (d) pfcnm remark set the alternate functions in the following sequence. <1> set the pfcn and pfcen registers. <2> set the pfcn register. <3> set the intrn or intfn register (to specify an external interrupt pin). if the pmcn register is set first, an unintende d function may be set while the pfcn and pfcen registers are being set. chapter 4 port functions user?s manual u16603ej5v1ud 104 4.3.1 port 0 port 0 is a 7-bit port for which i/o settings can be controlled in 1-bit units. port 0 includes the following alternate-function pins. table 4-4. port 0 alternate-function pins pin name pin no. alternate-function pin name i/o remark block type p00 6 tip61/top61 i/o g-1 p01 7 tip60/top60 i/o g-1 p02 17 nmi input l-1 p03 18 intp0/adtrg input n-1 p04 19 intp1 input l-1 p05 20 intp2/drst note input aa-1 p06 21 intp3 input selectable as n-ch open-drain output l-1 note the drst pin is for on-chip debugging (flash memory version only). if on-chip debugging is not used, fix the p05/intp2/drs t pin to low level between when the reset signal of the reset pin is released and when the ocdm.ocdm0 bit is cleared (0). although the mask rom versions do not support the on-chip debug mode, an on-chip pull-down resistor is incorporated. handle the p05/intp2 pin the same as in flash memory versions. for details, see 4.6.3 cautions on on-chip debug pins . caution the p00 to p06 pins have h ysteresis characteristics in the input mode of the alternate function, but do not have hysteresis characteristics in the port mode. (1) port 0 register (p0) 0 outputs 0 outputs 1 p0n 0 1 output data control (in output mode) (n = 0 to 6) p0 p06 p05 p04 p03 p02 p01 p00 after reset: 00h (output latch) r/w address: fffff400h chapter 4 port functions user?s manual u16603ej5v1ud 105 (2) port 0 mode register (pm0) 1 output mode input mode pm0n 0 1 i/o mode control (n = 0 to 6) pm0 pm06 pm05 pm04 pm03 pm02 pm01 pm00 after reset: ffh r/w address: fffff420h (3) port 0 mode control register (pmc0) 0 pmc0 pmc06 pmc05 pmc04 pmc03 pmc02 pmc01 pmc00 i/o port intp3 input pmc06 0 1 specification of p06 pin operation mode i/o port intp2 input pmc05 0 1 specification of p05 pin operation mode i/o port intp1 input pmc04 0 1 specification of p04 pin operation mode i/o port intp0 input/adtrg input pmc03 0 1 specification of p03 pin operation mode i/o port nmi input pmc02 0 1 specification of p02 pin operation mode i/o port tip60 input/top60 output pmc01 0 1 specification of p01 pin operation mode i/o port tip61 input/top61 output pmc00 0 1 specification of p00 pin operation mode after reset: 00h r/w address: fffff440h caution the p05/intp2/drst pin becomes the drst pin regardless of the value of the pmc05 bit when the ocdm.ocdm0 bit = 1. chapter 4 port functions user?s manual u16603ej5v1ud 106 (4) port 0 function control register (pfc0) pfc0 after reset: 00h r/w address: fffff460h 0 0 0 0 pfc03 0 pfc01 pfc00 intp0 input adtrg input pfc03 0 1 specification of p03 pin alternate function tip60 input top60 output pfc01 0 1 specification of p01 pin alternate function tip61 input top61 output pfc00 0 1 specification of p00 pin alternate function (5) port 0 function register (pf0) 0 normal output (cmos output) n-ch open drain output pf0n 0 1 control of normal output or n-ch open-drain output (n = 0 to 6) pf0 pf06 pf05 pf04 pf03 pf02 pf01 pf00 after reset: 00h r/w address: fffffc60h caution to pull up an output pin at a voltage of ev dd or higher, be sure to set the corresponding pf0n bit to 1. chapter 4 port functions user?s manual u16603ej5v1ud 107 4.3.2 port 1 port 1 is a 2-bit port for which i/o settings can be controlled in 1-bit units. port 1 includes the following alternate-function pins. table 4-5. port 1 alternate-function pins pin name pin no. alternate-function pin name i/o remark block type p10 3 ano0 output ? a-2 p11 4 ano1 output ? a-2 caution when the power is turned on, the p10 and p11 pins may mome ntarily output an undefined level. (1) port 1 register (p1) 0 outputs 0 outputs 1 p1n 0 1 output data control (in output mode) (n = 0, 1) p1 0 0 0 0 0 p11 p10 after reset: 00h (output latch) r/w address: fffff402h caution do not read/write the p1 register during d/a conversion (see 14.4.3 cautions). (2) port 1 mode register (pm1) 1 output mode input mode pm1n 0 1 i/o mode control (n = 0, 1) pm1 1 1 1 1 1 pm11 pm10 after reset: ffh r/w address: fffff422h cautions 1. when using p1n as the alternate functi on (anon pin output), set the pm1n bit to 1. 2. when using one of the p10 and p11 pins as an i/o port and the other as a d/a output pin, do so in an application where th e port i/o level does not change during d/a output. chapter 4 port functions user?s manual u16603ej5v1ud 108 4.3.3 port 3 port 3 is a 10-bit port for which i/o settings can be controlled in 1-bit units. port 3 includes the following alternate-function pins. table 4-6. port 3 alternate-function pins pin name pin no. alternate-function pin name i/o remark block type p30 25 txda0/sob4 output g-3 p31 26 rxda0/intp7/sib4 input n-3 p32 27 ascka0/sckb4/tip00/top00 i/o u-1 p33 28 tip01/top01/ctxd1 note 1 i/o u-2 p34 29 tip10/top10/crxd1 note 1 i/o u-3 p35 30 tip11/top11 i/o u-4 p36 31 ctxd0 note 2 /ietx0 note 3 output g-3 p37 32 crxd0 note 2 /ierx0 note 3 input g-4 p38 35 txda2/sda00 note 4 i/o g-12 p39 36 rxda2/scl00 note 4 i/o selectable as n-ch open-drain output g-6 notes 1. can controller (2-channel) version only 2. can controller version only 3. iebus controller version only 4. i 2 c bus version (y products) only caution the p31 to p35 and p37 to p39 pins have hysteresis characteri stics in the input mode of the alternate-function pin, but do not have the h ysteresis characteristics in the port mode. (1) port 3 register (p3) outputs 0 outputs 1 p3n 0 1 output data control (in output mode) (n = 0 to 9) p3 (p3h) after reset: 0000h (output latch) r/w address: p3 fffff406h, p3l fffff406h, p3h fffff407h 0 0 0 0 0 0 p39 p38 p37 p36 p35 p34 p33 p32 p31 p30 8 9 10 11 12 13 14 15 (p3l) remarks 1. the p3 register can be read or written in 16-bit units. however, when using the higher 8 bits of t he p3 register as the p3h register and the lower 8 bits as the p3l register, p3 can be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of the p3 register in 8- bit or 1-bit units, specify them as bits 0 to 7 of the p3h register. chapter 4 port functions user?s manual u16603ej5v1ud 109 (2) port 3 mode register (pm3) 1 output mode input mode pm3n 0 1 i/o mode control (n = 0 to 9) 1 1 1 1 1 pm39 pm38 pm37 pm36 pm35 pm34 pm33 pm32 pm31 pm30 after reset: ffffh r/w address: pm3 fffff426h, pm3l fffff426h, pm3h fffff427h 8 9 10 11 12 13 14 15 pm3 (pm3h) (pm3l) remarks 1. the pm3 register can be read or written in 16-bit units. however, when using the higher 8 bits of t he pm3 register as the pm3h register and the lower 8 bits as the pm3l register, pm3 can be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of the pm3 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pm3h register. (3) port 3 mode control register (pmc3) (1/2) i/o port rxda2 input/scl00 i/o pmc39 0 1 specification of p39 pin operation mode i/o port txda2 output/sda00 i/o pmc38 0 1 specification of p38 pin operation mode after reset: 0000h r/w address: pmc3 fffff446h, pmc3l fffff446h, pmc3h fffff447h pmc37 pmc36 pmc35 pmc34 pmc33 pmc32 pmc31 pmc30 0 0 0 0 0 0 pmc39 pmc38 8 9 10 11 12 13 14 15 pmc3 (pmc3h) (pmc3l) chapter 4 port functions user?s manual u16603ej5v1ud 110 (2/2) i/o port tip11 input/top11 output pmc35 0 1 specification of p35 pin operation mode i/o port tip10 input/top10 output/crxd1 input pmc34 0 1 specification of p34 pin operation mode i/o port crxd0 input/ierx0 input pmc37 0 1 specification of p37 pin operation mode i/o port ctxd0 output/ietx0 output pmc36 0 1 specification of p36 pin operation mode i/o port tip01 input/top01 output/ctxd1 output pmc33 0 1 specification of p33 pin operation mode i/o port ascka0 input/sckb4 i/o/tip00 input/top00 output pmc32 0 1 specification of p32 pin operation mode i/o port rxda0 input/sib4 input/intp7 input pmc31 0 1 specification of p31 pin operation mode i/o port txda0 output/sob4 output pmc30 0 1 specification of p30 pin operation mode remarks 1. the pmc3 register can be read or written in 16-bit units. however, when using the higher 8 bits of th e pmc3 register as the pmc3h register and the lower 8 bits as the pmc3l register, pmc3 can be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of the pmc3 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pmc3h register. chapter 4 port functions user?s manual u16603ej5v1ud 111 (4) port 3 function control register (pfc3) after reset: 0000h r/w address: pfc3 fffff466h, pfc3l fffff466h, pfc3l fffff467h 0 0 0 0 0 0 pfc39 pfc38 pfc37 pfc36 pfc35 pfc34 pfc33 pfc32 pfc31 pfc30 8 9 10 11 12 13 14 15 pfc3 (pfc3h) (pfc3l) remarks 1. for details of alternate function specification, see 4.3.3 (6) port 3 alternate function specifications . 2. the pfc3 register can be read or written in 16-bit units. however, when using the higher 8 bits of t he pfc3 register as the pfc3h register and the lower 8 bits as the pfc3l register, pfc3 ca n be read or written in 8-bit and 1-bit units. 3. to read/write bits 8 to 15 of the pfc3 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pfc3h register. (5) port 3 function control ex pansion register l (pfce3l) pfce3l after reset: 00h r/w address: fffff706h 0 0 0 pfce34 pfce33 pfce32 0 0 remark for details of alternate function specification, see 4.3.3 (6) port 3 alternate function specifications . (6) port 3 alternate function specifications pfc39 specification of p39 pin alternate function 0 rxda2 input 1 scl00 input pfc38 specification of p38 pin alternate function 0 txda2 output 1 sda00 i/o pfc37 specification of p37 pin alternate function 0 crxd0 input 1 ierx0 input chapter 4 port functions user?s manual u16603ej5v1ud 112 pfc36 specification of p36 pin alternate function 0 ctxd0 output 1 ietx0 output pfc35 specification of p35 pin alternate function 0 tip11 input 1 top11 output pfce34 pfc3 specification of p34 pin alternate function 0 0 tip10 input 0 1 top10 output 1 0 crxd1 input 1 1 setting prohibited pfce33 pfc33 specification of p33 pin alternate function 0 0 tip01 input 0 1 top01 output 1 0 ctxd1 output 1 1 setting prohibited pfce32 pfc32 specification of p32 pin alternate function 0 0 ascka0 input 0 1 sckb4 i/o 1 0 tip00 input 1 1 top00 output pfc31 specification of p31 pin alternate function 0 rxda0 input/intp7 note input 1 sib4 input pfc30 specification of p30 pin alternate function 0 txda0 output 1 sob4 output note the intp7 pin and rxda0 pin are alternate-function pins. when using the pin as the rxda0 pin, disable edge detection for the intp7 alternate-function pin. (clear the intf3.intf31 bit and the intr3.intr31 bit to 0.) when using the pin as the intp7 pin, stop uarta0 reception. (clear the ua0ctl0.ua0rxe bit to 0.) chapter 4 port functions user?s manual u16603ej5v1ud 113 (7) port 3 function register (pf3) after reset: 0000h r/w address: pf3 fffffc66h, pf3l fffffc66h, pf3h fffffc67h pf37 pf36 pf35 pf34 pf33 pf32 pf31 pf30 0 0 0 0 0 0 pf39 pf38 8 9 10 11 12 13 14 15 normal output (cmos output) n-ch open-drain output pf3n 0 1 control of normal output or n-ch open-drain output (n = 0 to 9) pf3 (pf3h) (pf3l) caution to pull up an output pin at a voltage of ev dd or higher, be sure to set the corresponding pf3n bit to 1. remarks 1. the pf3 register can be read or written in 16-bit units. however, when using the higher 8 bits of the pf 3 register as the pf3h register and the lower 8 bits as the pf3l register, pf3 can be re ad or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of the pf3 register in 8-bit or 1-bit uni ts, specify them as bits 0 to 7 of the pf3h register. chapter 4 port functions user?s manual u16603ej5v1ud 114 4.3.4 port 4 port 4 is a 3-bit port that controls i/o in 1-bit units. port 4 includes the following alternate-function pins. table 4-7. port 4 alternate-function pins pin name pin no. alternate-function pin name i/o remark block type p40 22 sib0/sda01 note i/o g-6 p41 23 sob0/scl01 note i/o g-12 p42 24 sckb0 i/o selectable as n-ch open-drain output e-3 note i 2 c bus versions (y products) only caution the p40 to p42 pins have hysteresis characteri stics in the input mode of the alternate-function pin, but do not have the hysteresis characteristics in the port mode. (1) port 4 register (p4) 0 outputs 0 outputs 1 p4n 0 1 output data control (in output mode) (n = 0 to 2) p4 0 0 0 0 p42 p41 p40 after reset: 00h (output latch) r/w address: fffff408h (2) port 4 mode register (pm4) 1 output mode input mode pm4n 0 1 i/o mode control (n = 0 to 2) pm4 1 1 1 1 pm42 pm41 pm40 after reset: ffh r/w address: fffff428h chapter 4 port functions user?s manual u16603ej5v1ud 115 (3) port 4 mode control register (pmc4) 0 pmc4 0 0 0 0 pmc42 pmc41 pmc40 i/o port sckb0 i/o pmc42 0 1 specification of p42 pin operation mode i/o port sob0 output/scl01 i/o pmc41 0 1 specification of p41 pin operation mode i/o port sib0 input/sda01 i/o pmc40 0 1 specification of p40 pin operation mode after reset: 00h r/w address: fffff448h (4) port 4 function control register (pfc4) pfc4 after reset: 00h r/w address: fffff468h 0 0 0 0 0 0 pfc41 pfc40 sob0 output scl01 i/o pfc41 0 1 specification of p41 pin alternate function sib0 input sda01 i/o pfc40 0 1 specification of p40 pin alternate function chapter 4 port functions user?s manual u16603ej5v1ud 116 (5) port 4 function register (pf4) 0 normal output (cmos output) n-ch open-drain output pf4n 0 1 control of normal output or n-ch open-drain output (n = 0 to 2) pf4 0 0 0 0 pf42 pf41 pf40 after reset: 00h r/w address: fffffc68h caution to pull up an output pin at a voltage of ev dd or higher, be sure to set the corresponding pf4n bit to 1. chapter 4 port functions user?s manual u16603ej5v1ud 117 4.3.5 port 5 port 5 is a 6-bit port that controls i/o in 1-bit units. port 5 includes the following alternate-function pins. table 4-8. port 5 alternate-function pins pin name pin no. alternate-function pin name i/o remark block type p50 37 tiq01/kr0/toq01/rtp00 i/o u-5 p51 38 tiq02/kr1/toq02/rtp01 i/o u-5 p52 39 tiq03/kr2/toq03/rtp02/ddi note i/o u-6 p53 40 sib2/kr3/tiq00/toq00/rtp03/ddo note i/o u-7 p54 41 sob2/kr4/rtp04/dck note i/o u-8 p55 42 sckb2/kr5/rtp05/dms note i/o selectable as n-ch open-drain output u-9 note the ddi, ddo, dck, and dms pins are for on-chip debugging (flash memory version only). if on-chip debugging is not used, fix the p05/intp2/drs t pin to low level between when the reset signal of the reset pin is released and when the ocdm.ocdm0 bit is cleared (0). although the mask rom versions do not support the on-chip debug mode, an on-chip pull-down resistor is incorporated. handle the p05/intp2 pin the same as the flash memory versions. for details, see 4.6.3 cautions on on-chip debug pins . cautions 1. when the power is turned on, the p53 pin may mome ntarily output an undefined level. 2. the p50 to p55 pins have hysteresis characteristics in th e input mode of the alternate function, but do not have hysteresis characteristics in the port mode. (1) port 5 register (p5) 0 outputs 0 outputs 1 p5n 0 1 output data control (in output mode) (n = 0 to 5) p5 0 p55 p54 p53 p52 p51 p50 after reset: 00h (output latch) r/w address: fffff40ah chapter 4 port functions user?s manual u16603ej5v1ud 118 (2) port 5 mode register (pm5) 1 output mode input mode pm5n 0 1 i/o mode control (n = 0 to 5) pm5 1 pm55 pm54 pm53 pm52 pm51 pm50 after reset: ffh r/w address: fffff42ah (3) port 5 mode control register (pmc5) 0 pmc5 0 pmc55 pmc54 pmc53 pmc52 pmc51 pmc50 i/o port sckb2 i/o/kr5 input/rtp05 output pmc55 0 1 specification of p55 pin operation mode i/o port sob2 output/kr4 input/rtp04 output pmc54 0 1 specification of p54 pin operation mode i/o port sib2 input/kr3 input/tiq00 input/toq00 output/rtp03 output pmc53 0 1 specification of p53 pin operation mode i/o port tiq03 input/kr2 input/toq03 output/rtp02 output pmc52 0 1 specification of p52 pin operation mode i/o port tiq02 input/kr1 input/toq02 output/rtp01 output pmc51 0 1 specification of p51 pin operation mode i/o port tiq01 input/kr0 input/toq01 output/rtp00 output pmc50 0 1 specification of p50 pin operation mode after reset: 00h r/w address: fffff44ah chapter 4 port functions user?s manual u16603ej5v1ud 119 (4) port 5 function control register (pfc5) 0 pfc5 0 pfc55 pfc54 pfc53 pfc52 pfc51 pfc50 after reset: 00h r/w address: fffff46ah remark for details of alternate function specification, see 4.3.5 (6) port 5 alternate function specifications . (5) port 5 function control expansion register (pfce5) 0 pfce5 0 pfce55 pfce54 pfce53 pfce52 pfce51 pfce50 after reset: 00h r/w address: fffff70ah remark for details of alternate function specification, see 4.3.5 (6) port 5 alternate function specifications . (6) port 5 alternate function specifications pfce55 pfc55 specification of p55 pin alternate function 0 0 sckb2 i/o 0 1 kr5 input 1 0 setting prohibited 1 1 rtp05 output pfce54 pfc54 specification of p54 pin alternate function 0 0 sob2 output 0 1 kr4 input 1 0 setting prohibited 1 1 rtp04 output pfce53 pfc53 specification of p53 pin alternate function 0 0 sib2 input 0 1 tiq00 input/kr3 note input 1 0 toq00 output 1 1 rtp03 output chapter 4 port functions user?s manual u16603ej5v1ud 120 pfce52 pfc52 specification of p52 pin alternate function 0 0 setting prohibited 0 1 tiq03 input/kr2 note input 1 0 toq03 input 1 1 rtp02 output pfce51 pfc51 specification of p51 pin alternate function 0 0 setting prohibited 0 1 tiq02 input/kr1 note input 1 0 toq02 output 1 1 rtp01 output pfce50 pfc50 specification of p50 pin alternate function 0 0 setting prohibited 0 1 tiq01 input/kr0 note input 1 0 toq01 output 1 1 rtp00 output note the krn pin and tiq0m pin are alternate-function pins. when using the pin as the tiq0m pin, disable krn pin key return detection, which is the al ternate function. (clear the krm.krmn bit to 0.) also, when using the pin as the krn pin, disable tiq0m pin edge detection, which is the alternate function (n = 0 to 3, m = 0 to 3). pin name use as tiq0m pin use as krn pin kr0/tiq01 krm.krm0 bit = 0 tq0ioc1. tq0tig2, tq0ioc1. tq0tig3 bits = 0 kr1/tiq02 krm.krm1 bit = 0 tq0ioc1.tq0tig4, tq0ioc1.tq0tig5 bits = 0 kr2/tiq03 krm.krm2 bit = 0 tq0ioc1.tq0tig6, tq0ioc1.tq0tig7 bits = 0 kr3/tiq00 krm.krm3 bit = 0 tq0ioc1.tq0tig0, tq0ioc1.tq0tig1 bits = 0 tq0ioc2.tq0ees0, tq0ioc2.tq0ees1 bits = 0 tq0ioc2.tq0ets0, tq0ioc2.tq0ets1 bits = 0 (7) port 5 function register (pf5) 0 normal output (cmos output) n-ch open-drain output pf5n 0 1 control of normal output or n-ch open-drain output (n = 0 to 5) pf5 0 pf55 pf54 pf53 pf52 pf51 pf50 after reset: 00h r/w address: fffffc6ah caution to pull up an output pin at a voltage of ev dd or higher, be sure to set the corresponding pf5n bit to 1. chapter 4 port functions user?s manual u16603ej5v1ud 121 4.3.6 port 6 port 6 is a 16-bit port for which i/o settings can be controlled in 1-bit units. port 6 includes the following alternate-function pins. table 4-9. port 6 alternate-function pins pin name pin no. alternate-function pin name i/o remark block type p60 43 rtp10 output e-2 p61 44 rtp11 output e-2 p62 45 rtp12 output e-2 p63 46 rtp13 output e-2 p64 47 rtp14 output e-2 p65 48 rtp15 output e-2 p66 49 sib5 input e-1 p67 50 sob5 output e-2 p68 51 sckb5 i/o e-3 p69 52 tip70/top70 i/o g-1 p610 53 tip71 input e-1 p611 54 top71 output e-2 p612 55 tip80/top80 i/o g-1 p613 56 tip81/top81 i/o g-1 p614 57 ? ? c-1 p615 58 ? ? selectable as n-ch open-drain output c-1 caution the p66, p68 to p610, p612, and p613 pins have hysteresis ch aracteristics in the input mode of the alternate-function pin, but do not have th e hysteresis characteristics in the port mode. chapter 4 port functions user?s manual u16603ej5v1ud 122 (1) port 6 register (p6) outputs 0 outputs 1 p6n 0 1 output data control (in output mode) (n = 0 to 15) p6 (p6h) after reset: 0000h (output latch) r/w address: p6 fffff40ch, p6l fffff40ch, p6h fffff40dh p615 p614 p613 p612 p611 p610 p69 p68 p67 p66 p65 p64 p63 p62 p61 p60 8 9 10 11 12 13 14 15 (p6l) remarks 1. the p6 register can be read or written in 16-bit units. however, when using the higher 8 bits of t he p6 register as the p6h register and the lower 8 bits as the p6l register, p6 can be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of the p6 register in 8- bit or 1-bit units, specify them as bits 0 to 7 of the p6h register. (2) port 6 mode register (pm6) pm615 output mode input mode pm6n 0 1 i/o mode control (n = 0 to 15) pm614 pm613 pm612 pm611 pm610 pm69 pm68 pm67 pm66 pm65 pm64 pm63 pm62 pm61 pm60 after reset: ffffh r/w address: pm6 fffff42ch, pm6l fffff42ch, pm6h fffff42dh 8 9 10 11 12 13 14 15 pm6 (pm6h) (pm6l) remarks 1. the pm6 register can be read or written in 16-bit units. however, when using the higher 8 bits of t he pm6 register as the pm6h register and the lower 8 bits as the pm6l register, pm6 can be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of the pm6 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pm6h register. chapter 4 port functions user?s manual u16603ej5v1ud 123 (3) port 6 mode control register (pmc6) i/o port tip81 input/top81 output pmc613 0 1 specification of p613 pin operation mode i/o port tip80 input/top80 output pmc612 0 1 specification of p612 pin operation mode after reset: 0000h r/w address: pmc6 fffff44ch, pmc6l fffff44ch, pmc6h fffff44dh pmc67 pmc66 pmc65 pmc64 pmc63 pmc62 pmc61 pmc60 0 0 pmc613 pmc612 pmc611 pmc610 pmc69 pmc68 8 9 10 11 12 13 14 15 pmc6 (pmc6h) (pmc6l) i/o port tip70 input/top70 output pmc69 0 1 specification of p69 pin operation mode i/o port sckb5 i/o pmc68 0 1 specification of p68 pin operation mode i/o port top71 output pmc611 0 1 specification of p611 pin operation mode i/o port tip71 input pmc610 0 1 specification of p610 pin operation mode i/o port sob5 output pmc67 0 1 specification of p67 pin operation mode i/o port sib5 input pmc66 0 1 specification of p66 pin operation mode i/o port rtp1m i/o pmc6m 0 1 specification of p6m pin operation mode (m = 0 to 5) remarks 1. the pmc6 register can be read or written in 16-bit units. however, when using the higher 8 bits of th e pmc6 register as the pmc6h register and the lower 8 bits as the pmc6l register, pmc6 can be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of the pmc6 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pmc6h register. chapter 4 port functions user?s manual u16603ej5v1ud 124 (4) port 6 function control register h (pfc6h) 0 pfc6h 0 pfc613 pfc612 0 0 pfc69 0 tip81 input top81 output pfc613 0 1 specification of p613 pin operation mode tip80 input top80 output pfc612 0 1 specification of p612 pin operation mode tip70 input top70 output pfc69 0 1 specification of p69 pin operation mode after reset: 00h r/w address: fffff46dh 8 9 10 11 12 13 14 15 (5) port 6 function register (pf6) after reset: 0000h r/w address: pf6 fffffc6ch, pf6l fffffc6ch, pf6h fffffc6dh pf67 pf66 pf65 pf64 pf63 pf62 pf61 pf60 pf615 pf614 pf613 pf612 pf611 pf610 pf69 pf68 8 9 10 11 12 13 14 15 normal output (cmos output) n-ch open-drain output pf6n 0 1 control of normal output or n-ch open-drain output (n = 0 to 15) pf6 (pf6h) (pf6l) caution to pull up an output pin at a voltage of ev dd or higher, be sure to set the corresponding pf6n bit to 1. remarks 1. the pf6 register can be read or written in 16-bit units. however, when using the higher 8 bits of the pf 6 register as the pf6h register and the lower 8 bits as the pf6l register, pf6 can be re ad or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of the pf6 register in 8-bit or 1-bit uni ts, specify them as bits 0 to 7 of the pf6h register. chapter 4 port functions user?s manual u16603ej5v1ud 125 4.3.7 port 7 port 7 is a 16-bit port for which i/o settings can be controlled in 1-bit units. port 7 includes the following alternate-function pins. table 4-10. port 7 alternate-function pins pin name pin no. alternate-function pin name i/o remark block type p70 144 ani0 input a-1 p71 143 ani1 input a-1 p72 142 ani2 input a-1 p73 141 ani3 input a-1 p74 140 ani4 input a-1 p77 139 ani5 input a-1 p76 138 ani6 input a-1 p77 137 ani7 input a-1 p78 136 ani8 input a-1 p79 135 ani9 input a-1 p710 134 ani10 input a-1 p711 133 ani11 input a-1 p712 132 ani12 input a-1 p713 131 ani13 input a-1 p714 130 ani14 input a-1 p715 129 ani15 input ? a-1 chapter 4 port functions user?s manual u16603ej5v1ud 126 (1) port 7 register h, port 7 register l (p7h, p7l) outputs 0 outputs 1 p7n 0 1 output data control (in output mode) (n = 0 to 15) p7h p7l after reset: 00h (output latch) r/w address: p7l fffff40eh, p7h fffff40fh p77 p76 p75 p74 p73 p72 p71 p70 p715 p714 p713 p712 p711 p710 p79 p78 caution do not read/write the p7h and p7l regist ers during a/d conversion (see 13.6 (4) alternate i/o). remark these registers cannot be accessed in 16-bit units as the p7 register. they can be read or written in 8-bit or 1-bit units as the p7h and p7l registers. (2) port 7 mode register h, port 7 mode register l (pm7h, pm7l) pm715 output mode input mode pm7n 0 1 i/o mode control (n = 0 to 15) pm7h pm7l pm714 pm713 pm712 pm711 pm710 pm79 pm78 pm77 pm76 pm75 pm74 pm73 pm72 pm71 pm70 after reset: ffh r/w address: pm7l fffff42eh, pm7h fffff42fh caution when using the p7n pin as its alternate function (anin pin), set the pm7n bit to 1. remark these registers cannot be accessed in 16-bit units as the pm7 register. they can be read or written in 8-bit or 1-bit units as the pm7h and pm7l registers. chapter 4 port functions user?s manual u16603ej5v1ud 127 4.3.8 port 8 port 8 is a 2-bit port that controls i/o in 1-bit units. port 8 includes the following alternate-function pins. table 4-11. port 8 alternate-function pins pin name pin no. alternate-function pin name i/o remark block type p80 59 rxda3/intp8 input l-2 p81 60 txda3 output selectable as n-ch open-drain output e-2 caution the p80 pin has hysteresis char acteristics in the input mode of the alternate-function pin, but do not have the hysteresis characteristics in the port mode. (1) port 8 register (p8) 0 outputs 0 outputs 1 p8n 0 1 output data control (in output mode) (n = 0, 1) p8 0 0 0 0 0 p81 p80 after reset: 00h (output latch) r/w address: fffff410h (2) port 8 mode register (pm8) 1 output mode input mode pm8n 0 1 i/o mode control (n = 0, 1) pm8 1 1 1 1 1 pm81 pm80 after reset: ffh r/w address: fffff430h chapter 4 port functions user?s manual u16603ej5v1ud 128 (3) port 8 mode control register (pmc8) 0 pmc4 0 0 0 0 0 pmc81 pmc80 i/o port txda3 output pmc81 0 1 specification of p81 pin operation mode i/o port rxda3 input/intp8 note input pmc80 0 1 specification of p80 pin operation mode after reset: 00h r/w address: fffff450h note the intp8 and rxda3 pins are alternate-functi on pins. when using the rxda3 pin, disable detection of the edge of the intp8 pin (intf8.intf80 bit = 0 and intr8.intr80 bit = 0). when using the intp8 pin, stop the reception oper ation of uarta3 (ua3ctl0.ua3rxe bit = 0). (4) port 8 function register (pf8) 0 normal output (cmos output) n-ch open-drain output pf8n 0 1 control of normal output or n-ch open-drain output (n = 0, 1) pf8 0 0 0 0 0 pf81 pf80 after reset: 00h r/w address: fffffc70h caution to pull up an output pin at a voltage of ev dd or higher, be sure to set the corresponding pf8n bit to 1. chapter 4 port functions user?s manual u16603ej5v1ud 129 4.3.9 port 9 port 9 is a 16-bit port for which i/o settings can be controlled in 1-bit units. port 9 includes the following alternate-function pins. table 4-12. port 9 alternate-function pins pin name pin no. alternate-function pin name i/o remark block type p90 61 a0/kr6/txda1/sda02 note i/o u-10 p91 62 a1/kr7/rxda1/scl02 note i/o u-11 p92 63 a2/tip41/top41 i/o u-12 p93 64 a3/tip40/top40 i/o u-12 p94 65 a4/tip31/top31 i/o u-12 p95 66 a5/tip30/top30 i/o u-12 p96 67 a6/tip21/top21 i/o u-13 p97 68 a7/sib1/tip20/top20 i/o u-14 p98 69 a8/sob1 output g-3 p99 70 a9/sckb1 i/o g-5 p910 71 a10/sib3 i/o g-2 p911 72 a11/sob3 output g-3 p912 73 a12/sckb3 i/o g-5 p913 74 a13/intp4 i/o n-2 p914 75 a14/intp5/tip51/top51 i/o u-15 p915 76 a15/intp6/tip50/top50 i/o selectable as n-ch open-drain output u-15 note i 2 c bus versions (y products) only caution the p90 to p97, p99, p910, and p912 to p 915 pins have hysteresis char acteristics in the input mode of the alternate-function pin, but do not ha ve the hysteresis characteristics in the port mode. chapter 4 port functions user?s manual u16603ej5v1ud 130 (1) port 9 register (p9) p915 outputs 0 outputs 1 p9n 0 1 output data control (in output mode) (n = 0 to 15) p914 p913 p912 p911 p910 p99 p98 after reset: 0000h (output latch) r/w address: p9 fffff412h, p9l fffff412h, p9h fffff413h p97 p96 p95 p94 p93 p92 p91 p90 8 9 10 11 12 13 14 15 p9 (p9h) (p9l) remarks 1. the p9 register can be read or written in 16-bit units. however, when using the higher 8 bits of t he p9 register as the p9h register and the lower 8 bits as the p9l register, p9 can be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of the p9 register in 8- bit or 1-bit units, specify them as bits 0 to 7 of the p9h register. (2) port 9 mode register (pm9) pm97 output mode input mode pm9n 0 1 i/o mode control (n = 0 to 15) pm96 pm95 pm94 pm93 pm92 pm91 pm90 after reset: ffffh r/w address: pm9 fffff432h, pm9l fffff432h, pm9h fffff433h pm915 pm914 pm913 pm912 pm911 pm910 pm99 pm98 8 9 10 11 12 13 14 15 pm9 (pm9h) (pm9l) remarks 1. the pm9 register can be read or written in 16-bit units. however, when using the higher 8 bits of t he pm9 register as the pm9h register and the lower 8 bits as the pm9l register, pm9 can be read or written in 8-bit and 1-bit units. 2. to read/write bits 8 to 15 of the pm9 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pm9h register. chapter 4 port functions user?s manual u16603ej5v1ud 131 (3) port 9 mode control register (pmc9) (1/2) i/o port a15 output/intp6 input/tip50 input/top50 output pmc915 0 1 specification of p915 pin operation mode pmc97 pmc96 pmc95 pmc94 pmc93 pmc92 pmc91 pmc90 after reset: 0000h r/w address: pmc9 fffff452h, pmc9l fffff452h, pmc9h fffff453h pmc915 pmc914 pmc913 pmc912 pmc911 pmc910 pmc99 pmc98 i/o port a14 output/intp5 input/tip51 input/top51 output pmc914 0 1 specification of p914 pin operation mode i/o port a11 output/sob3 output pmc911 0 1 specification of p911 pin operation mode i/o port a10 output/sib3 input pmc910 0 1 specification of p910 pin operation mode i/o port a9 output/sckb1 i/o pmc99 0 1 specification of p99 pin operation mode i/o port a13 output/intp4 input pmc913 0 1 specification of p913 pin operation mode i/o port a12 output/sckb3 i/o pmc912 0 1 specification of p912 pin operation mode 8 9 10 11 12 13 14 15 pmc9 (pmc9h) (pmc9l) remarks 1. the pmc9 register can be read or written in 16-bit units. however, when using the higher 8 bits of th e pmc9 register as the pmc9h register and the lower 8 bits as the pmc9l register, pmc9 can be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of the pmc9 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pmc9h register. chapter 4 port functions user?s manual u16603ej5v1ud 132 (2/2) i/o port a8 output/sob1 output pmc98 0 1 specification of p98 pin operation mode i/o port a7 output/sib1 input/tip20 input/top20 output pmc97 0 1 specification of p97 pin operation mode i/o port a6 output/tip21 input/top21 output pmc96 0 1 specification of p96 pin operation mode i/o port a5 output/tip30 input/top30 output pmc95 0 1 specification of p95 pin operation mode i/o port a4 output/tip31 input/top31 output pmc94 0 1 specification of p94 pin operation mode i/o port a3 output/tip40 input/top40 output pmc93 0 1 specification of p93 pin operation mode i/o port a2 output/tip41 input/top41 output pmc92 0 1 specification of p92 pin operation mode i/o port a1 output/kr7 input/rxda1 input/scl02 i/o pmc91 0 1 specification of p91 pin operation mode i/o port a0 output/kr6 input/txda1 output/sda02 i/o pmc90 0 1 specification of p90 pin operation mode caution port 9 pins cannot be used as port pins or other alternate-function pins if even one of the a0 to a15 pins is used in the separate bus mode. afte r setting the pfc9 and pfce9 registers to 0000h, theref ore, set all 16 bits of the pmc9 re gister to ffffh at once. if even one of the a0 to a15 pins is not used in th e separate bus mode, port 9 pins can be used as port pins or other alte rnate-function pins. chapter 4 port functions user?s manual u16603ej5v1ud 133 (4) port 9 function control register (pfc9) caution port 9 pins cannot be used as port pins or ot her alternate-function pins if even one of the a0 to a15 pins is used in the separate bus mode . after setting the pfc9 and pfce9 registers to 0000h, therefore, set all 16 bits of th e pmc9 register to ffffh at once. if even one of the a0 to a15 pins is not used in the separate bus mode, port 9 pins can be used as port pins or other alternate-function pins. after reset: 0000h r/w address: pfc9 fffff472h, pfc9l fffff472h, pfc9h fffff473h pfc97 pfc96 pfc95 pfc94 pfc93 pfc92 pfc91 pfc90 pfc915 pfc914 pfc913 pfc912 pfc911 pfc910 pfc99 pfc98 8 9 10 11 12 13 14 15 pfc9 (pfc9h) (pfc9l) remarks 1. for details of alternate function specification, see 4.3.9 (6) port 9 alternate function specifications . 2. the pfc9 register can be read or written in 16-bit units. however, when using the higher 8 bits of t he pfc9 register as the pfc9h register and the lower 8 bits as the pfc9l register, pfc9 ca n be read or written in 8-bit or 1-bit units. 3. to read/write bits 8 to 15 of the pfc9 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pfc9h register. (5) port 9 function control expansion register (pfce9) after reset: 0000h r/w address: pfce9 fffff712h, pfce9l fffff712h, pfce9h fffff713h pfce97 pfce96 pfce95 pfce94 pfce93 pfce92 pfce91 pfce90 pfce915 pfce914 0 0 0 0 0 0 8 9 10 11 12 13 14 15 pfce9 (pfce9h) (pfce9l) remarks 1. for details of alternate function specification, see 4.3.9 (6) port 9 alternate function specifications . 2. the pfce9 register can be read or written in 16-bit units. however, when using the higher 8 bits of the pfce9 register as the pf ce9h register and the lower 8 bits as the pfce9l register, pfce9 c an be read or written in 8-bit or 1-bit units. 3. to read/write bits 8 to 15 of the pfce9 register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pfce9h register. chapter 4 port functions user?s manual u16603ej5v1ud 134 (6) port 9 alternate function specifications pfce915 pfc915 specification of p915 pin alternate function 0 0 a15 output 0 1 intp6 input 1 0 tip50 input 1 1 top50 output pfce914 pfc914 specification of p914 pin alternate function 0 0 a14 output 0 1 intp5 input 1 0 tip51 input 1 1 top51 output pfc913 specification of p913 pin alternate function 0 a13 output 1 intp4 input pfc912 specification of p912 pin alternate function 0 a12 output 1 sckb3 i/o pfc911 specification of p911 pin alternate function 0 a11 output 1 sob3 output pfc910 specification of p910 pin alternate function 0 a10 output 1 sib3 input pfc99 specification of p99 pin alternate function 0 a9 output 1 sckb1 i/o pfc98 specification of p98 pin alternate function 0 a8 output 1 sob1 output pfce97 pfc97 specification of p97 pin alternate function 0 0 a7 output 0 1 sib1 input 1 0 tip20 input 1 1 top20 output chapter 4 port functions user?s manual u16603ej5v1ud 135 pfce96 pfc96 specification of p96 pin alternate function 0 0 a6 output 0 1 setting prohibited 1 0 tip21 input 1 1 top21 output pfce95 pfc95 specification of p95 pin alternate function 0 0 a5 output 0 1 tip30 input 1 0 top30 output 1 1 setting prohibited pfce94 pfc94 specification of p94 pin alternate function 0 0 a4 output 0 1 tip31 input 1 0 top31 output 1 1 setting prohibited pfce93 pfc93 specification of p93 pin alternate function 0 0 a3 output 0 1 tip40 input 1 0 top40 output 1 1 setting prohibited pfce92 pfc92 specification of p92 pin alternate function 0 0 a2 output 0 1 tip41 input 1 0 top41 output 1 1 setting prohibited pfce91 pfc91 specification of p91 pin alternate function 0 0 a1 output 0 1 kr7 input 1 0 rxda1 input/kr7 input note 1 1 scl02 i/o pfce90 pfc90 specification of p90 pin alternate function 0 0 a0 output 0 1 kr6 input 1 0 txda1 output 1 1 sda02 i/o note the rxda1 and kr7 pins must not be used at the same time. when using the rxda1 pin, do not use the kr7 pin. when using the kr7 pin, do not use the rx da1 pin (it is recommended to set the pfc91 bit to 1 and clear the pfce91 bit to 0). chapter 4 port functions user?s manual u16603ej5v1ud 136 (7) port 9 function register (pf9) after reset: 0000h r/w address: pf3 fffffc72h, pf9l fffffc72h, pf9h fffffc73h pf97 pf96 pf95 pf94 pf93 pf92 pf91 pf90 pf915 pf914 pf913 pf912 pf911 pf910 pf99 pf98 normal output (cmos output) n-ch open-drain output pf9n 0 1 control of normal output or n-ch open-drain output (n = 0 to 15) 8 9 10 11 12 13 14 15 pf9 (pf9h) (pf9l) caution to pull up an output pin at a voltage of ev dd or higher, be sure to set the corresponding pf9n bit to 1. remarks 1. the pf9 register can be read or written in 16-bit units. however, when using the higher 8 bits of the pf 9 register as the pf9h register and the lower 8 bits as the pf9l register, pf9 can be re ad or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of the pf9 register in 8-bit or 1-bit uni ts, specify them as bits 0 to 7 of the pf9h register. chapter 4 port functions user?s manual u16603ej5v1ud 137 4.3.10 port cd port cd is a 4-bit port that controls i/o in 1-bit units. port cd includes the following alternate-function pins. table 4-13. port cd alternate-function pins pin name pin no. alternate-function pin name i/o remark block type pcd0 77 ? ? b-1 pcd1 78 ? ? b-1 pcd2 79 ? ? b-1 pcd3 80 ? ? ? b-1 (1) port cd register (pcd) 0 outputs 0 outputs 1 pcdn 0 1 output data control (in output mode) (n = 0 to 3) pcd 0 0 0 pcd3 pcd2 pcd1 pcd0 after reset: 00h (output latch) r/w address: fffff00eh (2) port cd mode register (pmcd) 1 output mode input mode pmcdn 0 1 i/o mode control (n = 0 to 3) pmcd 1 1 1 pmcd3 pmcd2 pmcd1 pmcd0 after reset: ffh r/w address: fffff02eh chapter 4 port functions user?s manual u16603ej5v1ud 138 4.3.11 port cm port cm is a 6-bit port for which i/o setti ngs can be controlled in 1-bit units. port cm includes the following alternate-function pins. table 4-14. port cm alternate-function pins pin name pin no. alternate-function pin name i/o remark block type pcm0 85 wait input d-1 pcm1 86 clkout output d-2 pcm2 87 hldak output d-2 pcm3 88 hldrq input d-1 pcm4 89 ? ? b-1 pcm5 90 ? ? ? b-1 (1) port cm register (pcm) 0 outputs 0 outputs 1 pcmn 0 1 output data control (in output mode) (n = 0 to 5) pcm 0 pcm5 pcm4 pcm3 pcm2 pcm1 pcm0 after reset: 00h (output latch) r/w address: fffff00ch (2) port cm mode register (pmcm) 1 output mode input mode pmcmn 0 1 i/o mode control (n = 0 to 5) pmcm 1 pmcm5 pmcm4 pmcm3 pmcm2 pmcm1 pmcm0 after reset: ffh r/w address: fffff02ch chapter 4 port functions user?s manual u16603ej5v1ud 139 (3) port cm mode control register (pmccm) 0 pmccm 0 0 0 pmccm3 pmccm2 pmccm1 pmccm0 i/o port hldrq input pmccm3 0 1 specification of pcm3 pin operation mode i/o port hldak output pmccm2 0 1 specification of pcm2 pin operation mode i/o port clkout output pmccm1 0 1 specification of pcm1 pin operation mode i/o port wait input pmccm0 0 1 specification of pcm0 pin operation mode after reset: 00h r/w address: fffff04ch chapter 4 port functions user?s manual u16603ej5v1ud 140 4.3.12 port cs port cs is an 8-bit port for which i/o se ttings can be controll ed in 1-bit units. port cs includes the following alternate-function pins. table 4-15. port cs alternate-function pins pin name pin no. alternate-function pin name i/o remark block type pcs0 81 cs0 output d-2 pcs1 82 cs1 output d-2 pcs2 83 cs2 output d-2 pcs3 84 cs3 output d-2 pcs4 91 ? ? b-1 pcs5 92 ? ? b-1 pcs6 93 ? ? b-1 pcs7 94 ? ? ? b-1 (1) port cs register (pcs) pcs7 outputs 0 outputs 1 pcsn 0 1 output data control (in output mode) (n = 0 to 7) pcs pcs6 pcs5 pcs4 pcs3 pcs2 pcs1 pcs0 after reset: 00h (output latch) r/w address: fffff008h (2) port cs mode register (pmcs) output mode input mode pmcsn 0 1 i/o mode control (n = 0 to 7) pmcs pmcs5 pmcs7 pmcs6 pmcs4 pmcs3 pmcs2 pmcs1 pmcs0 after reset: ffh r/w address: fffff028h chapter 4 port functions user?s manual u16603ej5v1ud 141 (3) port cs mode control register (pmccs) 0 pmccs 0 0 0 pmccs3 pmccs2 pmccs1 pmccs0 i/o port cs3 output pmccs3 0 1 specification of pcs3 pin operation mode i/o port cs2 output pmccs2 0 1 specification of pcs2 pin operation mode i/o port cs1 output pmccs1 0 1 specification of pcs1 pin operation mode i/o port cs0 output pmccs0 0 1 specification of pcs0 pin operation mode after reset: 00h r/w address: fffff048h chapter 4 port functions user?s manual u16603ej5v1ud 142 4.3.13 port ct port ct is an 8-bit port for which i/o se ttings can be controll ed in 1-bit units. port ct includes the following alternate-function pins. table 4-16. port ct alternate-function pins pin name pin no. alternate-function pin name i/o remark block type pct0 95 wr0 output d-2 pct1 96 wr1 output d-2 pct2 97 ? ? b-1 pct3 98 ? ? b-1 pct4 99 rd output d-2 pct5 100 ? ? b-1 pct6 101 astb output d-2 pct7 102 ? ? ? b-1 (1) port ct register (pct) pct7 outputs 0 outputs 1 pctn 0 1 output data control (in output mode) (n = 0 to 7) pct pct6 pct5 pct4 pct3 pct2 pct1 pct0 after reset: 00h (output latch) r/w address: fffff00ah (2) port ct mode register (pmct) pmct7 output mode input mode pmctn 0 1 i/o mode control (n = 0 to 7) pmct pmct6 pmct5 pmct4 pmct3 pmct2 pmct1 pmct0 after reset: ffh r/w address: fffff02ah chapter 4 port functions user?s manual u16603ej5v1ud 143 (3) port ct mode control register (pmcct) 0 pmcct pmcct6 0 pmcct4 0 0 pmcct1 pmcct0 i/o port astb output pmcct6 0 1 specification of pct6 pin operation mode i/o port rd output pmcct4 0 1 specification of pct4 pin operation mode i/o port wr1 output pmcct1 0 1 specification of pct1 pin operation mode i/o port wr0 output pmcct0 0 1 specification of pct0 pin operation mode after reset: 00h r/w address: fffff04ah chapter 4 port functions user?s manual u16603ej5v1ud 144 4.3.14 port dh port dh is an 8-bit port for which i/o setti ngs can be controlled in 1-bit units. port dh includes the following alternate-function pins. table 4-17. port dh alternate-function pins pin name pin no. alternate-function pin name i/o remark block type pdh0 121 a16 output d-2 pdh1 122 a17 output d-2 pdh2 123 a18 output d-2 pdh3 124 a19 output d-2 pdh4 125 a20 output d-2 pdh5 126 a21 output d-2 pdh6 127 a22 output d-2 pdh7 128 a23 output ? d-2 (1) port dh register (pdh) outputs 0 outputs 1 pdhn 0 1 output data control (in output mode) (n = 0 to 7) pdh after reset: 00h (output latch) r/w address: fffff006h pdh7 pdh6 pdh5 pdh4 pdh3 pdh2 pdh1 pdh0 (2) port dh mode register (pmdh) pmdh7 output mode input mode pmdhn 0 1 i/o mode control (n = 0 to 7) pmdh6 pmdh5 pmdh4 pmdh3 pmdh2 pmdh1 pmdh0 after reset: ffh r/w address: fffff026h pmdh chapter 4 port functions user?s manual u16603ej5v1ud 145 (3) port dh mode control register (pmcdh) i/o port am output (address bus output) (m = 16 to 23) pmcdhn 0 1 specification of pdhn pin operation mode (n = 0 to 7) pmcdh7 pmcdh6 pmcdh5 pmcdh4 pmcdh3 pmcdh2 pmcdh1 pmcdh0 after reset: 00h r/w address: fffff046h pmcdh chapter 4 port functions user?s manual u16603ej5v1ud 146 4.3.15 port dl port dl is a 16-bit port for which i/o se ttings can be controll ed in 1-bit units. port dl includes the following alternate-function pins. table 4-18. port dl alternate-function pins pin name pin no. alternate-function pin name i/o remark block type pdl0 105 ad0 i/o d-3 pdl1 106 ad1 i/o d-3 pdl2 107 ad2 i/o d-3 pdl3 108 ad3 i/o d-3 pdl4 109 ad4 i/o d-3 pdl5 110 ad5/flmd1 note i/o d-3 pdl6 111 ad6 i/o d-3 pdl7 112 ad7 i/o d-3 pdl8 113 ad8 i/o d-3 pdl9 114 ad9 i/o d-3 pdl10 115 ad10 i/o d-3 pdl11 116 ad11 i/o d-3 pdl12 117 ad12 i/o d-3 pdl13 118 ad13 i/o d-3 pdl14 119 ad14 i/o d-3 pdl15 120 ad15 i/o ? d-3 note since this pin is set in the flash memory progra mming mode, it does not need to be manipulated with the port control register. for details, see chapter 30 flash memory . (1) port dl register (pdl) pdl15 outputs 0 outputs 1 pdln 0 1 output data control (in output mode) (n = 0 to 15) pdl14 pdl13 pdl12 pdl11 pdl10 pdl9 pdl8 after reset: 0000h (output latch) r/w address: pdl fffff004h, pdll fffff004h, pdlh fffff005h pdl7 pdl6 pdl5 pdl4 pdl3 pdl2 pdl1 pdl0 8 9 10 11 12 13 14 15 pdl (pdlh) (pdll) remarks 1. the pdl register can be read or written in 16-bit units. however, when using the higher 8 bits of the pd l register as the pdlh register and the lower 8 bits as the pdll register, pdl can be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of the pdl register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pdlh register. chapter 4 port functions user?s manual u16603ej5v1ud 147 (2) port dl mode register (pmdl) pmdl7 output mode input mode pmdln 0 1 i/o mode control (n = 0 to 15) pmdl6 pmdl5 pmdl4 pmdl3 pmdl2 pmdl1 pmdl0 after reset: ffffh r/w address: pmdl fffff024h, pmdll fffff024h, pmdlh fffff025h pmdl15 pmdl14 pmdl13 pmdl12 pmdl11 pmdl10 pmdl9 pmdl8 8 9 10 11 12 13 14 15 pmdl (pmdlh) (pmdll) remarks 1. the pmdl register can be read or written in 16-bit units. however, when using the higher 8 bits of the pmdl register as the pmdlh register and the lower 8 bits as the pmdll register, pmdl can be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of the pmdl register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pmdlh register. (3) port dl mode control register (pmcdl) i/o port adn i/o (address/data bus i/o) pmcdln 0 1 specification of pdln pin operation mode (n = 0 to 15) pmcdl7 pmcdl6 pmcdl5 pmcdl4 pmcdl3 pmcdl2 pmcdl1 pmcdl0 after reset: 0000h r/w address: pmcdl fffff044h, pmcdll fffff044h, pmcdlh fffff045h pmcdl15 pmcdl14pmcdl13 pmcdl12 pmcdl11pmcdl10 pmcdl9 pmcdl8 8 9 10 11 12 13 14 15 pmcdl (pmcdlh) (pmcdll) caution when the smsel bit of the eximc register = 1 (separate mode) and the bs30 to bs00 bits of the bsc register = 0 (8-bit bus width) , do not specify the ad8 to ad15 pins. remarks 1. the pmcdl register can be read or written in 16-bit units. however, when using the higher 8 bits of the pmcdl register as the pmcdlh register and the lower 8 bits as the pmcdll register, pmcdl c an be read or written in 8-bit or 1-bit units. 2. to read/write bits 8 to 15 of the pmcdl register in 8-bit or 1-bit units, specify them as bits 0 to 7 of the pmcdlh register. chapter 4 port functions user?s manual u16603ej5v1ud 148 4.4 block diagrams figure 4-3. block diagram of type a-1 address rd a/d input signal wr pm pmmn wr port pmn pmn p-ch n-ch internal bus selector selector chapter 4 port functions user?s manual u16603ej5v1ud 149 figure 4-4. block diagram of type a-2 rd d/a output signal wr pm pmmn wr port pmn pmn p-ch n-ch internal bus selector selector address chapter 4 port functions user?s manual u16603ej5v1ud 150 figure 4-5. block diagram of type b-1 internal bus address rd wr pm pmmn wr port pmn pmn selector selector figure 4-6. block diagram of type c-1 internal bus address selector selector rd wr port pmn wr pf pfmn wr pm pmmn pmn ev dd ev ss p-ch n-ch chapter 4 port functions user?s manual u16603ej5v1ud 151 figure 4-7. block diagram of type d-1 wr port pmn wr pm pmmn wr pmc pmcmn rd input signal when alternate function is used pmn internal bus selector selector address chapter 4 port functions user?s manual u16603ej5v1ud 152 figure 4-8. block diagram of type d-2 wr port pmn wr pm pmmn wr pmc pmcmn rd output signal when alternate function is used pmn internal bus selector selector selector address chapter 4 port functions user?s manual u16603ej5v1ud 153 figure 4-9. block diagram of type d-3 wr port pmn wr pm pmmn wr pmc pmcmn rd pmn output signal when alternate function is used input signal when alternate function is used output enable signal of address/data bus input enable signal of address/data bus output buffer off signal internal bus selector selector selector selector address chapter 4 port functions user?s manual u16603ej5v1ud 154 figure 4-10. block diagram of type e-1 internal bus address input signal when alternate function is used selector selector rd wr port pmn wr pmc pmcmn wr pf pfmn wr pm pmmn pmn ev dd ev ss p-ch n-ch note note hysteresis characteristics are not available in port mode. chapter 4 port functions user?s manual u16603ej5v1ud 155 figure 4-11. block diagram of type e-2 internal bus address output signal when alternate function is used selector selector rd wr port pmn wr pmc pmcmn wr pf pfmn wr pm pmmn pmn ev dd ev ss p-ch n-ch selector chapter 4 port functions user?s manual u16603ej5v1ud 156 figure 4-12. block diagram of type e-3 rd wr port pmn wr pmc pmcmn wr pf pfmn wr pm pmmn pmn ev dd ev ss p-ch n-ch output signal when alternate function is used output enable signal when alternate function is used input signal when alternate function is used note internal bus selector selector selector address note hysteresis characteristics are not available in port mode. chapter 4 port functions user?s manual u16603ej5v1ud 157 figure 4-13. block diagram of type g-1 input signal when alternate function is used rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn output signal when alternate function is used pmn ev dd ev ss p-ch n-ch note internal bus selector selector selector address note hysteresis characteristics are not available in port mode. chapter 4 port functions user?s manual u16603ej5v1ud 158 figure 4-14. block diagram of type g-2 input signal when alternate function is used rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn output signal when alternate function is used pmn ev dd ev ss p-ch n-ch note internal bus selector selector selector address note hysteresis characteristics are not available in port mode. chapter 4 port functions user?s manual u16603ej5v1ud 159 figure 4-15. block diagram of type g-3 output signal 2 when alternate function is used rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn output signal 1 when alternate function is used pmn ev dd ev ss p-ch n-ch internal bus selector selector selector selector address chapter 4 port functions user?s manual u16603ej5v1ud 160 figure 4-16. block diagram of type g-4 rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn input signal 2 when alternate function is used input signal 1 when alternate function is used pmn ev dd ev ss p-ch n-ch note internal bus selector selector selector address note hysteresis characteristics are not available in port mode. chapter 4 port functions user?s manual u16603ej5v1ud 161 figure 4-17. block diagram of type g-5 rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn output signal 2 when alternate function is used output signal 1 when alternate function is used output enable signal when alternate function is used pmn ev dd ev ss p-ch n-ch input signal when alternate function is used note internal bus selector selector selector selector address note hysteresis characteristics are not available in port mode. chapter 4 port functions user?s manual u16603ej5v1ud 162 figure 4-18. block diagram of type g-6 output signal when alternate function is used input signal 1 when alternate function is used input signal 2 when alternate function is used note internal bus selector selector selector selector address rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn pmn ev dd ev ss p-ch n-ch note hysteresis characteristics are not available in port mode. chapter 4 port functions user?s manual u16603ej5v1ud 163 figure 4-19. block diagram of type g-12 input signal when alternate function is used output signal 1 when alternate function is used output signal 2 when alternate function is used note internal bus selector address rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn pmn ev dd ev ss p-ch n-ch selector selector selector note hysteresis characteristics are not available in port mode. chapter 4 port functions user?s manual u16603ej5v1ud 164 figure 4-20. block diagram of type l-1 input signal 1 when alternate function is used rd wr port pmn wr pmc pmcmn wr intr intrmn note 1 wr intf intfmn note 1 wr pf pfmn wr pm pmmn pmn ev dd ev ss p-ch n-ch edge detection noise elimination note 2 internal bus selector selector address notes 1. see 22.6 external interrupt request i nput pins (nmi and intp0 to intp7) . 2. hysteresis characteristics are not available in port mode. chapter 4 port functions user?s manual u16603ej5v1ud 165 figure 4-21. block diagram of type l-2 internal bus address input signal 1-1 when alternate function is used selector selector rd wr port pmn wr pmc pmcmn wr intr intrmn note 1 wr intf intfmn note 1 wr pf pfmn wr pm pmmn pmn input signal 1-2 when alternate function is used ev dd ev ss p-ch n-ch edge detection noise elimination note 2 notes 1. see 22.6 external interrupt request i nput pins (nmi and intp0 to intp8) . 2. hysteresis characteristics are not available in port mode. chapter 4 port functions user?s manual u16603ej5v1ud 166 figure 4-22. block diagram of type n-1 input signal 1 when alternate function is used rd wr port pmn wr pmc pmcmn wr intr intrmn note 1 wr intf intfmn note 1 wr pf pfmn wr pm wr pfc pfcmn pmmn pmn input signal 2 when alternate function is used ev dd ev ss p-ch n-ch edge detection noise elimination note 2 internal bus selector selector selector address notes 1. see 22.6 external interrupt request i nput pins (nmi and intp0 to intp8) . 2. hysteresis characteristics are not available in port mode. chapter 4 port functions user?s manual u16603ej5v1ud 167 figure 4-23. block diagram of type n-2 internal bus address input signal when alternate function is used selector selector selector rd wr port pmn wr pmc pmcmn wr intr intrmn note 1 wr intf intfmn note 1 wr pf pfmn wr pm wr pfc pfcmn pmmn pmn ev dd ev ss p-ch n-ch edge detection noise elimination note 2 output signal when alternate function is used notes 1. see 22.6 external interrupt request i nput pins (nmi and intp0 to intp8) . 2. hysteresis characteristics are not available in port mode. chapter 4 port functions user?s manual u16603ej5v1ud 168 figure 4-24. block diagram of type n-3 input signal 1-1 when alternate function is used input signal 1-2 when alternate function is used input signal 2 when alternate function is used rd wr port pmn wr pmc pmcmn wr intr intrmn note 1 wr intf intfmn note 1 wr pf pfmn wr pm wr pfc pfcmn pmmn pmn ev dd ev ss p-ch n-ch note 2 internal bus selector selector selector address edge detection noise elimination notes 1. see 22.6 external interrupt request i nput pins (nmi and intp0 to intp8) . 2. hysteresis characteristics are not available in port mode. chapter 4 port functions user?s manual u16603ej5v1ud 169 figure 4-25. block diagram of type u-1 input signal 2 when alternate function is used rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn input signal 1 when alternate function is used input signal 3 when alternate function is used output signal 2 when alternate function is used output signal 1 when alternate function is used output enable signal when alternate function is used pmn ev dd ev ss p-ch n-ch wr pfce pfcemn note internal bus selector selector selector selector selector address note hysteresis characteristics are not available in port mode. chapter 4 port functions user?s manual u16603ej5v1ud 170 figure 4-26. block diagram of type u-2 internal bus address input signal when alternate function is used selector selector selector rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn output signal 2 when alternate function is used output signal 3 when alternate function is used output signal 1 when alternate function is used pmn ev dd ev ss p-ch n-ch wr pfce pfcemn selector note note hysteresis characteristics are not available in port mode. chapter 4 port functions user?s manual u16603ej5v1ud 171 figure 4-27. block diagram of type u-3 internal bus address input signal 2 when alternate function is used selector selector selector rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn input signal 1 when alternate function is used input signal 3 when alternate function is used output signal 1 when alternate function is used pmn ev dd ev ss p-ch n-ch wr pfce pfcemn selector note note hysteresis characteristics are not available in port mode. chapter 4 port functions user?s manual u16603ej5v1ud 172 figure 4-28. block diagram of type u-4 internal bus address input signal when alternate function is used selector selector selector rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn output signal 2 when alternate function is used output signal 1 when alternate function is used pmn ev dd ev ss p-ch n-ch wr pfce pfcemn selector note note hysteresis characteristics are not available in port mode. chapter 4 port functions user?s manual u16603ej5v1ud 173 figure 4-29. block diagram of type u-5 input signal 1-1 when alternate function is used rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn input signal 1-2 when alternate function is used output signal 2 when alternate function is used output signal 1 when alternate function is used pmn ev dd ev ss p-ch n-ch wr pfce pfcemn note internal bus selector selector selector selector address noise elimination note hysteresis characteristics are not available in port mode. chapter 4 port functions user?s manual u16603ej5v1ud 174 figure 4-30. block diagram of type u-6 input signal 1-1 when alternate function is used rd wr port pmn wr pfc pfcmn wr pf pfmn wr ocdm0 ocdm0 wr pmc pmcmn wr pm pmmn input signal 1-2 when alternate function is used input signal when on-chip debugging pmn ev dd ev ss p-ch n-ch wr pfce pfcemn note internal bus selector selector selector selector address output signal 2 when alternate function is used output signal 1 when alternate function is used noise elimination note hysteresis characteristics are not available in port mode. chapter 4 port functions user?s manual u16603ej5v1ud 175 figure 4-31. block diagram of type u-7 input signal 1 when alternate function is used rd wr port pmn wr pfc pfcmn wr pf pfmn wr ocdm0 ocdm0 wr pmc pmcmn wr pm pmmn input signal 2-1 when alternate function is used input signal 2-2 when alternate function is used output signal when on-chip debugging pmn ev dd ev ss p-ch n-ch wr pfce pfcemn note internal bus selector selector selector selector selector selector address output signal 2 when alternate function is used output signal 1 when alternate function is used noise elimination note hysteresis characteristics are not available in port mode. chapter 4 port functions user?s manual u16603ej5v1ud 176 figure 4-32. block diagram of type u-8 input signal when alternate function is used rd wr port pmn wr pfc pfcmn wr pf pfmn wr ocdm0 ocdm0 wr pmc pmcmn wr pm pmmn input signal when on-chip debugging pmn ev dd ev ss p-ch n-ch wr pfce pfcemn note internal bus selector selector selector selector address output signal 2 when alternate function is used output signal 1 when alternate function is used noise elimination note hysteresis characteristics are not available in port mode. chapter 4 port functions user?s manual u16603ej5v1ud 177 figure 4-33. block diagram of type u-9 input signal 1 when alternate function is used rd wr port pmn wr pfc pfcmn wr pf pfmn wr ocdm0 ocdm0 wr pmc pmcmn wr pm pmmn input signal 2 when alternate function is used input signal when on-chip debugging output enable signal when alternate function is used pmn ev dd ev ss p-ch n-ch wr pfce pfcemn note internal bus selector selector selector selector selector address output signal 2 when alternate function is used output signal 1 when alternate function is used noise elimination note hysteresis characteristics are not available in port mode. chapter 4 port functions user?s manual u16603ej5v1ud 178 figure 4-34. block diagram of type u-10 internal bus address input signal 1 when alternate function is used selector selector selector selector rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn input signal 2 when alternate function is used output signal 2 when alternate function is used output signal 3 when alternate function is used output signal 1 when alternate function is used pmn ev dd ev ss p-ch n-ch wr pfce pfcemn noise elimination note selector note hysteresis characteristics are not available in port mode. chapter 4 port functions user?s manual u16603ej5v1ud 179 figure 4-35. block diagram of type u-11 internal bus address input signal 1 when alternate function is used selector selector selector selector rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn input signal 3 when alternate function is used output signal 2 when alternate function is used output signal 1 when alternate function is used pmn input signal 2 when alternate function is used ev dd ev ss p-ch n-ch wr pfce pfcemn noise elimination note selector note hysteresis characteristics are not available in port mode. chapter 4 port functions user?s manual u16603ej5v1ud 180 figure 4-36. block diagram of type u-12 input signal when alternate function is used rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn output signal 2 when alternate function is used output signal 1 when alternate function is used pmn ev dd ev ss p-ch n-ch wr pfce pfcemn note internal bus selector selector selector selector address note hysteresis characteristics are not available in port mode. chapter 4 port functions user?s manual u16603ej5v1ud 181 figure 4-37. block diagram of type u-13 input signal when alternate function is used rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn output signal 2 when alternate function is used output signal 1 when alternate function is used pmn ev dd ev ss p-ch n-ch wr pfce pfcemn note internal bus selector selector selector selector address note hysteresis characteristics are not available in port mode. chapter 4 port functions user?s manual u16603ej5v1ud 182 figure 4-38. block diagram of type u-14 input signal 1 when alternate function is used rd wr port pmn wr pfc pfcmn wr pf pfmn wr pmc pmcmn wr pm pmmn input signal 2 when alternate function is used output signal 2 when alternate function is used output signal 1 when alternate function is used pmn ev dd ev ss p-ch n-ch wr pfce pfcemn note internal bus selector selector selector selector address selector note hysteresis characteristics are not available in port mode. chapter 4 port functions user?s manual u16603ej5v1ud 183 figure 4-39. block diagram of type u-15 input signal 1 when alternate function is used input signal 2 when alternate function is used rd wr port pmn wr pmc pmcmn wr intr intrmn note 1 wr intf intfmn note 1 wr pf pfmn wr pm wr pfc pfcmn wr pfce pfcemn pmmn pmn ev dd ev ss p-ch n-ch output signal 2 when alternate function is used output signal 1 when alternate function is used note 2 internal bus selector selector selector selector address edge detection noise elimination selector notes 1. see 22.6 external interrupt request i nput pins (nmi and intp0 to intp8) . 2. hysteresis characteristics are not available in port mode. chapter 4 port functions user?s manual u16603ej5v1ud 184 figure 4-40. block diagram of type aa-1 rd wr port pmn wr intf intfmn note 1 wr pf pfmn wr ocdm0 ocdm0 wr pmc pmcmn wr pm pmmn pmn ev dd ev ss p-ch n-ch n-ch wr intr intrmn note 1 ev ss input signal when on-chip debugging external reset signal input signal when alternate function is used note 2 internal bus selector selector address edge detection noise elimination notes 1. see 22.6 external interrupt request i nput pins (nmi and intp0 to intp8) . 2. hysteresis characteristics are not available in port mode. chapter 4 port functions user?s manual u16603ej5v1ud 185 4.5 port register settings when alternate function is used table 4-19 shows the port register settings when each port is used for an alternate function. when using a port pin as an alternate-function pin, refer to the description of each pin. chapter 4 port functions 186 user?s manual u16603ej5v1ud table 4-19. using port pin as alternate-function pin (1/9) alternate function pin name name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) tip61 input p00 = setting not required pm00 = setting not required pmc00 = 1 ? pfc00 = 0 p00 top61 output p00 = setting not required pm00 = setting not required pmc00 = 1 ? pfc00 = 1 tip60 input p01 = setting not required pm01 = setting not required pmc01 = 1 ? pfc01 = 0 p01 top60 output p01 = setting not required pm01 = setting not required pmc01 = 1 ? pfc01 = 1 p02 nmi input p02 = setting not required pm02 = setting not required pmc02 = 1 ? ? intp0 input p03 = setting not required pm03 = setting not required pmc03 = 1 ? pfc03 = 0 p03 adtrg input p03 = setting not required pm03 = setting not required pmc03 = 1 ? pfc03 = 1 p04 intp1 input p04 = setting not required pm04 = setting not required pmc04 = 1 ? ? intp2 input p05 = setting not required pm05 = setting not required pmc05 = 1 ? ? p05 drst note 1 input p05 = setting not required pm05 = setting not required pmc05 = setting not required ? ? ocdm0 (ocdm) = 1 p06 intp3 input p06 = setting not required pm06 = setting not required pmc06 = 1 ? ? p10 ano0 output p10 = setting not required pm10 = 1 ? ? ? p11 ano1 output p11 = setting not required pm11 = 1 ? ? ? txda0 output p30 = setting not required pm30 = setting not required pmc30 = 1 ? pfc30 = 0 p30 sob4 output p30 = setting not required pm30 = setting not required pmc30 = 1 ? pfc30 = 1 rxda0 input p31 = setting not required pm31 = setting not required pmc31 = 1 ? note 2 , pfc31 = 0 intp7 input p31 = setting not required pm31 = setting not required pmc31 = 1 ? note 2 , pfc31 = 0 p31 sib4 input p31 = setting not required pm31 = setting not required pmc31 = 1 ? pfc31 = 1 ascka0 input p32 = setting not required pm32 = setting not required pmc32 = 1 pfce32 = 0 pfc32 = 0 sckb4 i/o p32 = setting not required pm32 = setting not required pmc32 = 1 pfce32 = 0 pfc32 = 1 tip00 input p32 = setting not required pm32 = setting not required pmc32 = 1 pfce32 = 1 pfc32 = 0 p32 top00 output p32 = setting not required pm32 = setting not required pmc32 = 1 pfce32 = 1 pfc32 = 1 notes 1. flash memory versions only 2. the intp7 pin and rxda0 pin are alternate-function pins. when using the pin as the rxda0 pin, disable edge detection for the alternate-function intp7 pin (clear the intf3.intf31 bit and intr3.intr31 bit to 0). when using the pin as the intp7 pin, stop the uarta0 reception ope ration (clear the ua0ctl0.ua0rxe bit to 0). caution when using one of the p10 and p11 pi ns as an i/o port and the other as a d/a out put pin (ano0, ano1), do so in an appli cation where the port i/o level does not change during d/a output. chapter 4 port functions user?s manual u16603ej5v1ud 187 table 4-19. using port pin as alternate-function pin (2/9) alternate function pin name name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) tip01 input p33 = setting not required pm33 = setting not required pmc33 = 1 pfce33 = 0 pfc33 = 0 top01 output p33 = setting not required pm33 = setting not required pmc33 = 1 pfce33 = 0 pfc33 = 1 p33 ctxd1 note 1 output p33 = setting not required pm33 = setting not required pmc33 = 1 pfce33 = 1 pfc33 = 0 tip10 input p34 = setting not required pm34 = setting not required pmc34 = 1 pfce34 = 0 pfc34 = 0 top10 input p34 = setting not required pm34 = setting not required pmc34 = 1 pfce34 = 0 pfc34 = 1 p34 crxd1 note 1 input p34 = setting not required pm34 = setting not required pmc34 = 1 pfce34 = 1 pfc34 = 0 tip11 input p35 = setting not required pm35 = setting not required pmc35 = 1 ? pfc35 = 0 p35 top11 output p35 = setting not required pm35 = setting not required pmc35 = 1 ? pfc35 = 1 ctxd0 note 2 output p36 = setting not required pm36 = setting not required pmc36 = 1 ? pfc36 = 0 p36 ietx0 note 3 output p36 = setting not required pm36 = setting not required pmc36 = 1 ? pfc36 = 1 crxd0 note 2 input p37 = setting not required pm37 = setting not required pmc37 = 1 ? pfc37 = 0 p37 ierx0 note 3 input p37 = setting not required pm37 = setting not required pmc37 = 1 ? pfc37 = 1 txda2 output p38 = setting not required pm38 = setting not required pmc38 = 1 ? pfc38 = 0 p38 sda00 note 4 i/o p38 = setting not required pm38 = setting not required pmc38 = 1 ? pfc38 = 1 pf38 (pf3) = 1 rxda2 input p39 = setting not required pm39 = setting not required pmc39 = 1 ? pfc39 = 0 p39 scl00 note 4 i/o p39 = setting not required pm39 = setting not required pmc39 = 1 ? pfc39 = 1 pf39 (pf3) = 1 sib0 input p40 = setting not required pm40 = setting not required pmc40 = 1 ? pfc40 = 0 p40 sda01 note 4 i/o p40 = setting not required pm40 = setting not required pmc40 = 1 ? pfc40 = 1 pf40 (pf4) = 1 sob0 output p41 = setting not required pm41 = setting not required pmc41 = 1 ? pfc41 = 0 p41 scl01 note 4 i/o p41 = setting not required pm41 = setting not required pmc41 = 1 ? pfc41 = 1 pf41 (pf4) = 1 p42 sckb0 i/o p42 = setting not required pm42 = setting not required pmc42 = 1 ? ? notes 1. can controller (2-channel) versions only 2. can controller versions only 3. iebus controller versions only 4. i 2 c bus versions (y products) only chapter 4 port functions 188 user?s manual u16603ej5v1ud table 4-19. using port pin as alternate-function pin (3/9) alternate function pin name name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) tiq01 input p50 = setting not required pm50 = setting not required pmc50 = 1 pfce50 = 0 pfc50 = 1 krm0 (krm) = 0 kr0 input p50 = setting not required pm50 = setting not required pmc50 = 1 pfce50 = 0 pfc50 = 1 tq0tig2, tq0tig3 (tq0ioc1) = 0 toq01 output p50 = setting not required pm50 = setting not required pmc50 = 1 pfce50 = 1 pfc50 = 0 p50 rtp00 output p50 = setting not required pm50 = setting not required pmc50 = 1 pfce50 = 1 pfc50 = 1 tiq02 input p51 = setting not required pm51 = setting not required pmc51 = 1 pfce51 = 0 pfc51 = 1 krm1 (krm) = 0 kr1 input p51 = setting not required pm51 = setting not required pmc51 = 1 pfce51 = 0 pfc51 = 1 tq0tig4, tq0tig5 (tq0ioc1) = 0 toq02 output p51 = setting not required pm51 = setting not required pmc51 = 1 pfce51 = 1 pfc51 = 0 p51 rtp01 output p51 = setting not required pm51 = setting not required pmc51 = 1 pfce51 = 1 pfc51 = 1 tiq03 input p52 = setting not required pm52 = setting not required pmc52 = 1 pfce52 = 0 pfc52 = 1 krm2 (krm) = 0 kr2 input p52 = setting not required pm52 = setting not required pmc52 = 1 pfce52 = 0 pfc52 = 1 tq0tig6, tq0tig7 (tq0i0c1) = 0 toq03 output p52 = setting not required pm52 = setting not required pmc52 = 1 pfce52 = 1 pfc52 = 0 rtp02 output p52 = setting not required pm52 = setting not required pmc52 = 1 pfce52 = 1 pfc52 = 1 p52 ddi note input p52 = setting not required pm52 = setting not required pmc52 = setting not required pfce52 = setting not required pfc52 = setting not required ocdm0 (ocdm) = 1 sib2 input p53 = setting not required pm53 = setting not required pmc53 = 1 pfce53 = 0 pfc53 = 0 tiq00 input p53 = setting not required pm53 = setting not required pmc53 = 1 pfce53 = 0 pfc53 = 1 krm3 (krm) = 0 kr3 input p53 = setting not required pm53 = setting not required pmc53 = 1 pfce53 = 0 pfc53 = 1 tq 0tig0, tq0tig1 (tq0ioc1) = 0, tq0ees0, tq0ees1 (tq0ioc2) = 0, tq0ets0, tq0ets1 (tq0ioc2) = 0 toq00 input p53 = setting not required pm53 = setting not required pmc53 = 1 pfce53 = 1 pfc53 = 0 rtp03 output p53 = setting not required pm53 = setting not required pmc53 = 1 pfce53 = 1 pfc53 = 1 p53 ddo note output p53 = setting not required pm53 = setting not required pmc53 = setting not required pfce53 = setting not required pfc53 = setting not required ocdm0 (ocdm) = 1 note flash memory versions only chapter 4 port functions user?s manual u16603ej5v1ud 189 table 4-19. using port pin as alternate function-pin (4/9) alternate function pin name name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) sob2 output p54 = setting not required pm54 = setting not required pmc54 = 1 pfce54 = 0 pfc54 = 0 kr4 input p54 = setting not required pm54 = setting not required pmc54 = 1 pfce54 = 0 pfc54 = 1 rtp04 output p54 = setting not required pm54 = setting not required pmc54 = 1 pfce54 = 1 pfc54 = 1 p54 dck note input p54 = setting not required pm54 = setting not required pmc54 = setting not required pfce54 = setting not required pfc54 = setting not required ocdm0 (ocdm) = 1 sckb2 i/o p55 = setting not required pm55 = setting not required pmc55 = 1 pfce55 = 0 pfc55 = 0 kr5 input p55 = setting not required pm55 = setting not required pmc55 = 1 pfce55 = 0 pfc55 = 1 rtp05 output p55 = setting not required pm55 = setting not required pmc55 = 1 pfce55 = 1 pfc55 = 1 p55 dms note input p55 = setting not required pm55 = setting not required pmc55 = setting not required pfce55 = setting not required pfc55 = setting not required ocdm0 (ocdm) = 1 p60 rtp10 output p60 = setting not required pm60 = setting not required pmc60 = 1 ? ? p61 rtp11 output p61 = setting not required pm61 = setting not required pmc61 = 1 ? ? p62 rtp12 output p62 = setting not required pm62 = setting not required pmc62 = 1 ? ? p63 rtp13 output p63 = setting not required pm63 = setting not required pmc63 = 1 ? ? p64 rtp14 output p64 = setting not required pm64 = setting not required pmc64 = 1 ? ? p65 rtp15 output p65 = setting not required pm65 = setting not required pmc65 = 1 ? ? p66 sib5 input p66 = setting not required pm66 = setting not required pmc66 = 1 ? ? p67 sob5 output p67 = setting not required pm67 = setting not required pmc67 = 1 ? ? p68 sckb5 i/o p68 = setting not required pm68 = setting not required pmc68 = 1 ? ? tip70 input p69 = setting not required pm69 = setting not required pmc69 = 1 ? pfc69 = 0 p69 top70 output p69 = setting not required pm69 = setting not required pmc69 = 1 ? pfc69 = 1 p610 tip71 input p610 = setting not required pm610 = setting not required pmc610 = 1 ? ? p611 top71 output p611 = setting not required pm611 = setting not required pmc611 = 1 ? ? tip80 input p612 = setting not required pm612 = setting not required pmc612 = 1 ? pfc612 = 0 p612 top80 output p612 = setting not required pm612 = setting not required pmc612 = 1 ? pfc612 = 1 tip81 input p613 = setting not required pm613 = setting not required pmc613 = 1 ? pfc613 = 0 p613 top81 output p613 = setting not required pm613 = setting not required pmc613 = 1 ? pfc613 = 1 note flash memory versions only chapter 4 port functions 190 user?s manual u16603ej5v1ud table 4-19. using port pin as alternate function-pin (5/9) alternate function pin name name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) p70 ani0 input p70 = setting not required pm70 = 1 ? ? ? p71 ani1 input p71 = setting not required pm71 = 1 ? ? ? p72 ani2 input p72 = setting not required pm72 = 1 ? ? ? p73 ani3 input p73 = setting not required pm73 = 1 ? ? ? p74 ani4 input p74 = setting not required pm74 = 1 ? ? ? p75 ani5 input p75 = setting not required pm75 = 1 ? ? ? p76 ani6 input p76 = setting not required pm76 = 1 ? ? ? p77 ani7 input p77 = setting not required pm77 = 1 ? ? ? p78 ani8 input p78 = setting not required pm78 = 1 ? ? ? p79 ani9 input p79 = setting not required pm79 = 1 ? ? ? p710 ani10 input p710 = setting not required pm710 = 1 ? ? ? p711 ani11 input p711 = setting not required pm711 = 1 ? ? ? p712 ani12 input p712 = setting not required pm712 = 1 ? ? ? p713 ani13 input p713 = setting not required pm713 = 1 ? ? ? p714 ani14 input p714 = setting not required pm714 = 1 ? ? ? p715 ani15 input p715 = setting not required pm715 = 1 ? ? ? rxda3 input p80 = setting not required pm80 = setting not required pmc80 = 1 ? ? note p80 intp8 input p80 = setting not required pm80 = setting not required pmc80 = 1 ? ? note p81 txda3 output p81 = setting not required pm81 = setting not required pmc81 = 1 ? ? note the intp8 pin and rxda3 pin are alternate-function pins. when using the pin as the rxda3 pin, disable edge detection for the alternate-function intp8 pin (clear the intf8.intf80 bit and the intr8.intr80 bit to 0). when using the pin as the intp8 pin, stop uarta3 reception operati on (clear the ua0ctl3.ua3rxe bit to 0). chapter 4 port functions user?s manual u16603ej5v1ud 191 table 4-19. using port pin as alternate-function pin (6/9) alternate function pin name name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) a0 output p90 = setting not required pm90 = setting not required pmc90 = 1 pfce90 = 0 pfc90 = 0 note 1 kr6 input p90 = setting not required pm90 = setting not required pmc90 = 1 pfce90 = 0 pfc90 = 1 txda1 output p90 = setting not required pm90 = setting not required pmc90 = 1 pfce90 = 1 pfc90 = 0 p90 sda02 note 2 i/o p90 = setting not required pm90 = setting not required pmc90 = 1 pfce90 = 1 pfc90 = 1 pf90 (pf9) = 1 a1 output p91 = setting not required pm91 = setting not required pmc91 = 1 pfce91 = 0 pfc91 = 0 note 1 kr7 input p91 = setting not required pm91 = setting not required pmc91 = 1 pfce91 = 0 pfc91 = 1 rxda1/kr7 note 3 input p91 = setting not required pm91 = setting not required pmc91 = 1 pfce91 = 1 pfc91 = 0 p91 scl02 note 2 i/o p91 = setting not required pm91 = setting not required pmc91 = 1 pfce91 = 1 pfc91 = 1 pf91 (pf9) = 1 a2 output p92 = setting not required pm92 = setting not required pmc92 = 1 pfce92 = 0 pfc92 = 0 note 1 tip41 input p92 = setting not required pm92 = setting not required pmc92 = 1 pfce92 = 0 pfc92 = 1 p92 top41 output p92 = setting not required pm92 = setting not required pmc92 = 1 pfce92 = 1 pfc92 = 0 a3 output p93 = setting not required pm93 = setting not required pmc93 = 1 pfce93 = 0 pfc93 = 0 note 1 tip40 input p93 = setting not required pm93 = setting not required pmc93 = 1 pfce93 = 0 pfc93 = 1 p93 top40 output p93 = setting not required pm93 = setting not required pmc93 = 1 pfce93 = 1 pfc93 = 0 a4 output p94 = setting not required pm94 = setting not required pmc94 = 1 pfce94 = 0 pfc94 = 0 note 1 tip31 input p94 = setting not required pm94 = setting not required pmc94 = 1 pfce94 = 0 pfc94 = 1 p94 top31 output p94 = setting not required pm94 = setting not required pmc94 = 1 pfce94 = 1 pfc94 = 0 a5 output p95 = setting not required pm95 = setting not required pmc95 = 1 pfce95 = 0 pfc95 = 0 note 1 tip30 input p95 = setting not required pm95 = setting not required pmc95 = 1 pfce95 = 0 pfc95 = 1 p95 top30 output p95 = setting not required pm95 = setting not required pmc95 = 1 pfce95 = 1 pfc95 = 0 notes 1. port 9 pins cannot be used as port pins or other alternate-func tion pins if even one of the a0 to a15 pins is used in the sepa rate bus mode. after setting the pfc9 and pfce9 registers to 0000h, therefore, set all 16 bits of the pmc9 register to ffffh at once. 2. i 2 c bus versions (y products) only 3. the rxda1 and kr7 pins must not be used at the same time. when using the rxda1 pin, do not use the kr7 pin. when using the kr 7 pin, do not use the rxda1 pin (it is recommended to set the pf c91 bit to 1 and clear the pfce91 bit to 0). chapter 4 port functions 192 user?s manual u16603ej5v1ud table 4-19. using port pin as alternate-function pin (7/9) alternate function pin name name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) a6 output p96 = setting not required pm96 = setting not required pmc96 = 1 pfce96 = 0 pfc96 = 0 note tip21 input p96 = setting not required pm96 = setting not required pmc96 = 1 pfce96 = 1 pfc96 = 0 p96 top21 output p96 = setting not required pm96 = setting not required pmc96 = 1 pfce96 = 1 pfc96 = 1 a7 output p97 = setting not required pm97 = setting not required pmc97 = 1 pfce97 = 0 pfc97 = 0 note sib1 input p97 = setting not required pm97 = setting not required pmc97 = 1 pfce97 = 0 pfc97 = 1 tip20 input p97 = setting not required pm97 = setting not required pmc97 = 1 pfce97 = 1 pfc97 = 0 p97 top20 output p97 = setting not required pm97 = setting not required pmc97 = 1 pfce97 = 1 pfc97 = 1 a8 output p98 = setting not required pm98 = setting not required pmc98 = 1 ? pfc98 = 0 note p98 sob1 output p98 = setting not required pm98 = setting not required pmc98 = 1 ? pfc98 = 1 a9 output p99 = setting not required pm99 = setting not required pmc99 = 1 ? pfc99 = 0 note p99 sckb1 i/o p99 = setting not required pm99 = setting not required pmc99 = 1 ? pfc99 = 1 a10 output p910 = setting not required pm910 = setting not required pmc910 = 1 ? pfc910 = 0 note p910 sib3 input p910 = setting not required pm910 = setting not required pmc910 = 1 ? pfc910 = 1 a11 output p911 = setting not required pm911 = setting not required pmc911 = 1 ? pfc911 = 0 note p911 sob3 output p911 = setting not required pm911 = setting not required pmc911 = 1 ? pfc911 = 1 a12 output p912 = setting not required pm912 = setting not required pmc912 = 1 ? pfc912 = 0 note p912 sckb3 i/o p912 = setting not required pm912 = setting not required pmc912 = 1 ? pfc912 = 1 a13 output p913 = setting not required pm913 = setting not required pmc913 = 1 ? pfc913 = 0 note p913 intp4 input p913 = setting not required pm913 = setting not required pmc913 = 1 ? pfc913 = 1 note port 9 pins cannot be used as port pins or other alternate-function pins if even one of the a0 to a15 pins is used in the sepa rate bus mode. after setting the pfc9 and pfce9 registers to 0000h, therefore, set all 16 bits of the pmc9 register to ffffh at once. chapter 4 port functions user?s manual u16603ej5v1ud 193 table 4-19. using port pin as alternate-function pin (8/9) alternate function pin name name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) a14 output p914 = setting not required pm914 = setting not required pmc914 = 1 pfce914 = 0 pfc914 = 0 note intp5 input p914 = setting not required pm914 = setting not required pmc914 = 1 pfce914 = 0 pfc914 = 1 tip51 input p914 = setting not required pm914 = setting not required pmc914 = 1 pfce914 = 1 pfc914 = 0 p914 top51 output p914 = setting not required pm914 = setting not required pmc914 = 1 pfce914 = 1 pfc914 = 1 a15 output p915 = setting not required pm915 = setting not required pmc915 = 1 pfce915 = 0 pfc915 = 0 note intp6 input p915 = setting not required pm915 = setting not required pmc915 = 1 pfce915 = 0 pfc915 = 1 tip50 input p915 = setting not required pm915 = setting not required pmc915 = 1 pfce915 = 1 pfc915 = 0 p915 top50 output p915 = setting not required pm915 = setting not required pmc915 = 1 pfce915 = 1 pfc915 = 1 pcs0 cs0 output pcs0 = setting not required pmcs0 = setting not required pmccs0 = 1 ? ? pcs1 cs1 output pcs1 = setting not required pmcs1 = setting not required pmccs1 = 1 ? ? pcs2 cs2 output pcs2 = setting not required pmcs2 = setting not required pmccs2 = 1 ? ? pcs3 cs3 output pcs3 = setting not required pmcs3 = setting not required pmccs3 = 1 ? ? pcm0 wait input pcm0 = setting not required pmcm0 = setting not required pmccm0 = 1 ? ? pcm1 clkout output pcm1 = setting not required pmcm1 = setting not required pmccm1 = 1 ? ? pcm2 hldak output pcm2 = setting not required pmcm2 = setting not required pmccm2 = 1 ? ? pcm3 hldrq input pcm3 = setting not required pmcm3 = setting not required pmccm3 = 1 ? ? pct0 wr0 output pct0 = setting not required pmct0 = setting not required pmcct0 = 1 ? ? pct1 wr1 output pct1 = setting not required pmct1 = setting not required pmcct1 = 1 ? ? pct4 rd output pct4 = setting not required pmct4 = setting not required pmcct4 = 1 ? ? pct6 astb output pct6 = setting not required pmct6 = setting not required pmcct6 = 1 ? ? note port 9 pins cannot be used as port pins or other alternate-function pins if even one of the a0 to a15 pins is used in the sepa rate bus mode. after setting the pfc9 and pfce9 registers to 0000h, therefore, set all 16 bits of the pmc9 register to ffffh at once. chapter 4 port functions 194 user?s manual u16603ej5v1ud table 4-19. using port pin as alternate-function pin (9/9) alternate function pin name name i/o pnx bit of pn register pmnx bit of pmn register pmcnx bit of pmcn register pfcenx bit of pfcen register pfcnx bit of pfcn register other bits (registers) pdh0 a16 output pdh0 = setting not required pmdh0 = setting not required pmcdh0 = 1 ? ? pdh1 a17 output pdh1 = setting not required pmdh1 = setting not required pmcdh1 = 1 ? ? pdh2 a18 output pdh2 = setting not required pmdh2 = setting not required pmcdh2 = 1 ? ? pdh3 a19 output pdh3 = setting not required pmdh3 = setting not required pmcdh3 = 1 ? ? pdh4 a20 output pdh4 = setting not required pmdh4 = setting not required pmcdh4 = 1 ? ? pdh5 a21 output pdh5 = setting not required pmdh5 = setting not required pmcdh5 = 1 ? ? pdh6 a22 output pdh6 = setting not required pmdh6 = setting not required pmcdh6 = 1 ? ? pdh7 a23 output pdh7 = setting not required pmdh7 = setting not required pmcdh7 = 1 ? ? pdl0 ad0 i/o pdl0 = setting not required pmdl0 = setting not required pmcdl0 = 1 ? ? pdl1 ad1 i/o pdl1 = setting not required pmdl1 = setting not required pmcdl1 = 1 ? ? pdl2 ad2 i/o pdl2 = setting not required pmdl2 = setting not required pmcdl2 = 1 ? ? pdl3 ad3 i/o pdl3 = setting not required pmdl3 = setting not required pmcdl3 = 1 ? ? pdl4 ad4 i/o pdl4 = setting not required pmdl4 = setting not required pmcdl4 = 1 ? ? ad5 i/o pdl5 = setting not required pmdl5 = setting not required pmcdl5 = 1 ? ? pdl5 flmd1 note input pdl5 = setting not required pmdl5 = setting not required pmcdl5 = setting not required ? ? pdl6 ad6 i/o pdl6 = setting not required pmdl6 = setting not required pmcdl6 = 1 ? ? pdl7 ad7 i/o pdl7 = setting not required pmdl7 = setting not required pmcdl7 = 1 ? ? pdl8 ad8 i/o pdl8 = setting not required pmdl8 = setting not required pmcdl8 = 1 ? ? pdl9 ad9 i/o pdl9 = setting not required pmdl9 = setting not required pmcdl9 = 1 ? ? pdl10 ad10 i/o pdl10 = setting not required pmdl10 = setting not required pmcdl10 = 1 ? ? pdl11 ad11 i/o pdl11 = setting not required pmdl11 = setting not required pmcdl11 = 1 ? ? pdl12 ad12 i/o pdl12 = setting not required pmdl12 = setting not required pmcdl12 = 1 ? ? pdl13 ad13 i/o pdl13 = setting not required pmdl13 = setting not required pmcdl13 = 1 ? ? pdl14 ad14 i/o pdl14 = setting not required pmdl14 = setting not required pmcdl14 = 1 ? ? pdl15 ad15 i/o pdl15 = setting not required pmdl15 = setting not required pmcdl15 = 1 ? ? note since this pin is set in the flash memory programming mode , it does not need to be manipulate d using the port control register . for details, see chapter 30 flash memory . chapter 4 port functions user?s manual u16603ej5v1ud 195 4.6 cautions 4.6.1 cautions on setting port pins (1) in the v850es/sj2 and v850es/sj2-h, the general-pur pose port function and several peripheral function i/o pin share a pin. to switch between the general-purpo se port (port mode) and the peripheral function i/o pin (alternate-function mode), set by the pmcn register. in regards to this register setting sequence, note with caution the following. (a) cautions on switching from por t mode to alternate-function mode to switch from the port mode to alternat e-function mode in the following order. <1> set the pfn register note : n-ch open-drain setting <2> set the pfcn and pfcen regist ers: alternate-function selection <3> set the corresponding bit of the pmcn regist er to 1: switch to alternate-function mode if the pmcn register is set first, not e with caution that, at that moment or depending on the change of the pin states in accordance with the setting of the pf n, pfcn, and pfcen register s, unexpected operations may occur. a concrete example is shown as example below. note n-ch open-drain output pin only caution regardless of the port mo de/alternate-function mode, the pn register is read and written as follows. ? pn register read: read the port output latc h value (when pmn.pmnm bit = 0), or read the pin states (pmn.pmnm bit = 1). ? pn register write: write to the port output latch [example] scl01 pin setting example the scl01 pin is used alternately with the p41/ sob0 pin. select the valid pin functions with the pmc4, pfc4, and pf4 registers. pmc41 bit pfc41 bit pf41 bit valid pin functions 0 don?t care 1 p41 (in output port mode, n-ch open-drain output) 0 1 sob0 output (n-ch open-drain output) 1 1 1 scl01 i/o (n-ch open-drain output) chapter 4 port functions user?s manual u16603ej5v1ud 196 the order of setting in which malfunction may occur on switching from the p41 pin to the scl01 pin are shown below. setting order setting contents pin states pin level <1> initial value (pmc41 bit = 0, pfc41 bit = 0, pf41 bit = 0) port mode (input) hi-z <2> pmc41 bit 1 sob0 output low level (high level depending on the csib0 setting) <3> pfc41 bit 1 scl01 i/o high level (cmos output) <4> pf41 bit 1 scl01 i/o hi-z (n-ch open-drain output) in <2>, i 2 c communication may be affected since the alternate-function sob0 output is output to the pin. in the cmos output period of <2 > or <3>, unnecessary current may be generated. (b) cautions on alternat e-function mode (input) the input signal to the alternate-function block is low level when the pmcn.pmcnm bit is 0 due to the and output of the pmcn register set value and the pin le vel. thus, depending on the port setting and alternate- function operation enable timing, unexpected operations may occur. therefore, switch between the port mode and alternate-function m ode in the following sequence. ? to switch from port mode to alternate-function mode (input) set the pins to the alternate-function mode usi ng the pmcn register and then enable the alternate- function operation. ? to switch from alternate-function mode (input) to port mode stop the alternate-function operation and then switch the pins to the port mode. the concrete examples are show n as example 1 and example 2. [example 1] switch from general-purpose port (p02) to external interrupt pin (nmi) when the p02/nmi pin is pulled up as shown in figure 4-41 and the rising edge is specified in the nmi pin edge detection setting, even though hi gh level is input continuously to the nmi pin during switching from the p02 pin to the an nmi pin (pmc02 bit = 0 1), this is detected as a rising edge as if the low level changed to high level, and an nmi interrupt occurs. to avoid it, set the nmi pin?s valid edge after switching from the p02 pin to the nmi pin. chapter 4 port functions user?s manual u16603ej5v1ud 197 figure 4-41. example of switching from p02 to nmi (incorrect) pmc0 nmi interrupt occurrence 76543 2 p02/nmi 3 v 10 0 1 pmc0m bit = 0: port mode pmc0m bit = 1: alternate-function mode rising edge detector pmc02 bit = 0: low level pmc02 bit = 1: high level remark m = 0 to 7 [example 2] switch from external pin (nmi) to general-purpose port (p02) when the p02/nmi pin is pulled up as shown in figure 4-42 and the falling edge is specified in the nmi pin edge detection setting, even though hi gh level is input continuously to the nmi pin at switching from the nmi pin to the p02 pin (pmc02 bit = 1 0), this is detected as falling edge as if high level changed to low level, and nmi interrupt occurs. to avoid this, set the nmi pin edge detection as ?no edge detected? before switching to the p02 pin. figure 4-42. example of switching from nmi to p02 (incorrect) pmc0 76543 2 p02/nmi 3 v 10 nmi interrupt occurrence 1 0 pmc0m bit = 0: port mode pmc0m bit = 1: alternate-function mode falling edge detector pmc02 bit = 1: high level pmc02 bit = 0: low level remark m = 0 to 7 (2) in port mode, the pfn.pfnm bit is valid only in t he output mode (pmn.pmnm bit = 0). in the input mode (pmnm bit = 1), the value of the pfnm bit is not reflected in the buffer. chapter 4 port functions user?s manual u16603ej5v1ud 198 4.6.2 cautions on bit manipulation instruction for port n register (pn) when a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the value of the output latch of an input port that is not subject to manipulation may be written in addition to the targeted bit. therefore, it is recommended to rewr ite the output latch when switching a port from input mode to output mode. chapter 4 port functions user?s manual u16603ej5v1ud 199 4.6.3 cautions on on-chip debug pins the drst, dck, dms, ddi, and ddo pins are on-chip debug pins (these pins are available only in the flash- memory versions). after reset by the reset pin, the p05/intp2/drst pin is in itialized to function as an on-chip debug pin (drst). if a high level is input to the drst pin at this time, the on-chip debug mode is set, and the dck, dms, ddi, and ddo pins can be used. the following action must be taken if on-chip debugging is not used. ? clear the ocdm0 bit of the ocdm register (special register) (0) at this time, fix the p05/intp2/drst pin to low level from when reset by the reset pin is released until the above action is taken. if a high level is input to the drst pin before the above ac tion is taken, it may cause a malfunction (cpu deadlock). handle the p05 pin with the utmost care. caution the p05/intp2/drst pin is not initialized to function as an on-chip debug pin (drst) when a reset signal (wdt2res) is generated due to a watc hdog timer overflow, a reset signal (lvires) is generated by the low-voltage detector (lvi), or a reset signal (clmres) is generated by the clock monitor (clm) (reset by the low-voltage detector (lvi) is available only in the v850es/sj2). the ocdm register holds the current value. 4.6.4 cautions on p05/intp2/drst pin the p05/intp2/drst pin has an internal pull-down resistor (30 k typ.). after a reset by the reset pin, a pull- down resistor is connected. the pull-down resistor is disconnected when the ocdm0 bit is cleared (0). 4.6.5 cautions on p10, p11, and p53 pins when power is turned on when the power is turned on, the following pins may momentarily output an undefined level. ? p10/ano0 pin ? p11/ano1 pin ? p53/sib2/kr3/tiq00/toq00/rtp03/ddo note pin note the ddo pin is provided only in the flash memory version. 4.6.6 hysteresis characteristics in port mode, the following port pins do not have hysteresis characteristics. p00 to p06 p31 to p35, p37 to p39 p40 to p42 p50 to p55 p66, p68 to p610, p612, p613 p80 p90 to p97, p99, p910, p912 to p915 4.6.7 cautions on separate bus mode port 9 pins cannot be used as port pins or other alternate-function pins if even one of the a0 to a15 pins is used in the separate bus mode. after setting the pfc9 and pfce9 registers to 0000h, ther efore, set all 16 bits of the pmc9 register to ffffh at once. if even one of the a0 to a15 pins is not used in the s eparate bus mode, port 9 pins can be used as port pins or other alternate-function pins. user?s manual u16603ej5v1ud 200 chapter 5 bus control function the v850es/sj2 and v850es/sj2-h are provided with an external bus interface function by which external memories such as rom and ra m, and i/o can be connected. 5.1 features output is selectable from a multiplexed bus with a mi nimum of 3 bus cycles and a separate bus with a minimum of 2 bus cycles. 8-bit/16-bit data bus selectable wait function ? programmable wait function of up to 7 states ? external wait function using wait pin idle state function bus hold function up to 16 mb of physical memory connectable the bus can be controlled at a voltage that is different fr om the operating voltage when bv dd ev dd = v dd . however, in separate bus mode, set bv dd = ev dd = v dd . chapter 5 bus control function user?s manual u16603ej5v1ud 201 5.2 bus control pins the pins used to connect an external device are listed in the table below. table 5-1. bus control pins (multiplexed bus) bus control pin alternate-function pin i/o function ad0 to ad15 pdl0 to pdl15 i/o address/data bus a16 to a23 pdh0 to pdh7 output address bus wait pcm0 input external wait control clkout pcm1 output internal system clock wr0, wr1 pct0, pct1 output write strobe signal rd pct4 output read strobe signal astb pct6 output address strobe signal hldrq pcm3 input hldak pcm2 output bus hold control cs0 to cs3 pcs0 to pcs3 output chip select table 5-2. external control pins (separate bus) bus control pin alternate-function pin i/o function ad0 to ad15 pdl0 to pdl15 i/o data bus a0 to a15 p90 to p915 output address bus a16 to a23 pdh0 to pdh7 output address bus wait pcm0 input external wait control clkout pcm1 output internal system clock wr0, wr1 pct0, pct1 output write strobe signal rd pct4 output read strobe signal hldrq pcm3 input hldak pcm2 output bus hold control cs0 to cs3 pcs0 to pcs3 output chip select 5.2.1 pin status when internal rom, intern al ram, or on-chip peripheral i/o is accessed when the internal rom, internal ram, or on-chip peripheral i/o are accessed, the status of each pin is as follows. table 5-3. pin statuses when in ternal rom, internal ram, or on-chip peripheral i/o is accessed separate bus mode multiplexed bus mode address bus (a23 to a0) undefined a ddress bus (a23 to a16) undefined data bus (ad15 to ad0) hi-z address/data bus (ad15 to ad0) undefined control signal (rd, wr0, wr1, cs0 to cs3) high level control signal (rd, wr0, wr1, cs0 to cs3, astb) high level caution when a write access is perfo rmed to the internal rom area, address, data, and control signals are activated in the same way as acce ss to the external memory area. 5.2.2 pin status in each operation mode for the pin status of the v850es/sj2 and v850es/sj2-h in each operation mode, see 2.2 pin status . chapter 5 bus control function user?s manual u16603ej5v1ud 202 5.3 memory block function the 16 mb external memory space is divided into memory blocks of (lower) 2 mb, 2 mb, 4 mb, and 8 mb. the programmable wait function and bus cycl e operation mode for each of these bloc ks can be independen tly controlled in one-block units. figure 5-1. data memory map: physical address (80 kb) use prohibited external memory area (8 mb) internal rom area note 4 (1 mb) external memory area (1 mb) internal ram area (60 kb) on-chip peripheral i/o area (4 kb) external memory area (4 mb) external memory area (2 mb) external memory area (2 mb) 03ffffffh 03fec000h 03febfffh 01000000h 00ffffffh 00800000h 007fffffh 00400000h 003fffffh 00200000h 001fffffh 00000000h 03ffffffh 03fff000h 03ffefffh 001fffffh 00100000h 000fffffh 00000000h use prohibited note 1 03ff0000h 03feffffh programmable peripheral i/o area note 2 or use prohibited note 3 03fef000h 03feefffh 03fec000h cs3 cs2 cs1 cs0 notes 1. use of addresses 03fef000h to 03feffffh is prohibited because these addresses are in the same area as the on-chip peripheral i/o area. 2. only the programmable peripheral i/o area is s een as images of 256 mb each in the 4 gb address space. 3. addresses 03fec000h to 03fecbffh are alloca ted to addresses 03fec000h to 03feefffh of the can controller version as a programmable per ipheral i/o area. use of these addresses in a version without a can controller is prohibited. 4. this area is an external memory area in the case of a data write access. chapter 5 bus control function user?s manual u16603ej5v1ud 203 5.4 external bus interface mode control function the v850es/sj2 and v850es/sj2-h have the following two external bus interface modes. ? multiplexed bus mode ? separate bus mode these two modes can be selected by using the eximc register. (1) external bus interface mode control register (eximc) the eximc register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 multiplexed bus mode separate bus mode smsel 0 1 mode selection eximc 0 0 0 0 0 0 smsel after reset: 00h r/w address: ffffffbeh caution set the eximc register fr om the internal rom or internal ram area before making an external access. after setting the eximc register, be sure to insert a nop instruction. chapter 5 bus control function user?s manual u16603ej5v1ud 204 5.5 bus access 5.5.1 number of clocks for access the following table shows the number of basic clocks required for accessing each resource. (1) in v850es/sj2 area (bus width) bus cycle type internal rom (32 bits) internal ram (32 bits) external memory (16 bits) instruction fetch (normal access) 1 1 note 1 3 + n note 2 instruction fetch (branch) 2 2 note 1 3 + n note 2 operand data access 3 1 3 + n note 2 notes 1. increases by 1 if a conflict with a data access occurs. 2. 2 + n clocks (n: number of wait states ) when the separate bus mode is selected. remark unit: clocks/access (2) in v850es/sj2-h area (bus width) bus cycle type internal rom (32 bits) internal ram (32 bits) external memory (16 bits) instruction fetch (normal access) 1 1 note 1 3 + n note 2 instruction fetch (branch) 3 2 note 1 3 + n note 2 operand data access 4 1 3 + n note 2 notes 1. increases by 1 if a conflict with a data access occurs. 2. 2 + n clocks (n: number of wait states ) when the separate bus mode is selected. remark unit: clocks/access chapter 5 bus control function user?s manual u16603ej5v1ud 205 5.5.2 bus size setting function each external memory area selected by csn can be set by using the bsc register. however, the bus size can be set to 8 bits and 16 bits only. the external memory areas of the v850es/sj2 and v8 50es/sj2-h are selected in memory cs0 to cs3. (1) bus size configuration register (bsc) the bsc register can be read or written in 16-bit units. reset sets this register to 5555h. caution write to the bsc register after reset, an d then do not change the set values. also, do not access an external memory area until the initial settings of the bsc register are complete. after reset: 5555h r/w address: fffff066h 0 0 bsn0 0 1 8 bits 16 bits bsc 1 bs30 0 0 1 bs20 0 0 1 bs10 0 0 1 bs00 8 9 10 11 12 13 data bus width of cs n space (n = 0 to 3) 14 15 1 2 3 4 5 6 7 0 cs0 cs3 cs2 cs1 caution be sure to set bits 14, 12, 10, and 8 to ?1?, and clear bits 15, 13, 11, 9, 7, 5, 3, and 1 to ?0?. chapter 5 bus control function user?s manual u16603ej5v1ud 206 5.5.3 access by bus size the v850es/sj2 and v850es/sj2-h access the on-chip peripheral i/o and extern al memory in 8-bi t, 16-bit, or 32- bit units. the bus size is as follows. ? the bus size of the on-chip peripheral i/o is fixed to 16 bits. ? the bus size of the external memory is selectable from 8 bits or 16 bits (by using the bsc register). the operation when each of the above is accessed is descr ibed below. all data is accessed starting from the lower side. the v850es/sj2 and v850es/sj2-h support only the little-endian format. figure 5-2. little-endian address in word 000bh 000ah 0009h 0008h 0007h 0006h 0005h 0004h 0003h 0002h 0001h 0000h 31 24 23 16 15 8 7 0 (1) data space the v850es/sj2 and v850es/sj2-h have an address misalign function. with this function, data can be placed at all addresse s, regardless of the format of the data (word data or halfword data). however, if the word data or halfword data is not aligned at the boundary, a bus cycle is generated at least twice, causing the bus efficiency to drop. (a) halfword-length data access a byte-length bus cycle is generated twice if t he least significant bit of the address is 1. (b) word-length data access (i) a byte-length bus cycle, halfword-length bus cycle, and byte-length bus cycle are generated in that order if the least significant bit of the address is 1. (ii) a halfword-length bus cycle is generated twic e if the lower 2 bits of the address are 10. chapter 5 bus control function user?s manual u16603ej5v1ud 207 (2) byte access (8 bits) (a) 16-bit data bus width <1> access to even address (2n) <2> access to odd address (2n + 1) 7 0 7 0 byte data 15 8 external data bus 2n address 7 0 7 0 15 8 2n + 1 address byte data external data bus (b) 8-bit data bus width <1> access to even address (2n) <2> access to odd address (2n + 1) 7 0 7 0 2n address byte data external data bus 7 0 7 0 2n + 1 address byte data external data bus chapter 5 bus control function user?s manual u16603ej5v1ud 208 (3) halfword access (16 bits) (a) with 16-bit data bus width <1> access to even address (2n) <2> access to odd address (2n + 1) 7 0 7 0 15 8 2n address 15 8 2n + 1 halfword data external data bus first access second access 7 0 7 0 15 8 15 8 7 0 7 0 15 8 15 8 2n + 2 halfword data external data bus 2n address halfword data external data bus address 2n + 1 (b) 8-bit data bus width <1> access to even address (2n) <2> access to odd address (2n + 1) first access second access 7 0 7 0 15 8 address 7 0 7 0 15 8 2n + 1 address 2n halfword data external data bus halfword data external data bus first access second access 7 0 7 0 15 8 7 0 7 0 15 8 2n + 2 2n + 1 address address halfword data external data bus halfword data external data bus chapter 5 bus control function user?s manual u16603ej5v1ud 209 (4) word access (32 bits) (a) 16-bit data bus width (1/2) <1> access to address (4n) first access second access 7 0 7 0 15 8 4n 15 8 4n + 1 23 16 31 24 7 0 7 0 15 8 4n + 2 15 8 4n + 3 23 16 31 24 word data external data bus address word data external data bus address <2> access to address (4n + 1) first access second access third access 7 0 7 0 15 8 15 8 4n + 1 23 16 31 24 7 0 7 0 15 8 4n + 2 15 8 4n + 3 23 16 31 24 7 0 7 0 15 8 4n + 4 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address chapter 5 bus control function user?s manual u16603ej5v1ud 210 (a) 16-bit data bus width (2/2) <3> access to address (4n + 2) first access second access 7 0 7 0 15 8 4n + 2 15 8 4n + 3 23 16 31 24 7 0 7 0 15 8 4n + 4 15 8 4n + 5 23 16 31 24 word data external data bus address word data external data bus address <4> access to address (4n + 3) first access second access third access 7 0 7 0 15 8 15 8 4n + 3 23 16 31 24 7 0 7 0 15 8 4n + 4 15 8 4n + 5 23 16 31 24 7 0 7 0 15 8 4n + 6 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address chapter 5 bus control function user?s manual u16603ej5v1ud 211 (b) 8-bit data bus width (1/2) <1> access to address (4n) first access second access third access fourth access 7 0 7 0 15 8 4n 23 16 31 24 7 0 7 0 4n + 1 15 8 23 16 31 24 7 0 7 0 4n + 2 15 8 23 16 31 24 7 0 7 0 4n + 3 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address word data external data bus address <2> access to address (4n + 1) first access second access third access fourth access 7 0 7 0 15 8 4n + 1 23 16 31 24 7 0 7 0 4n + 2 15 8 23 16 31 24 7 0 7 0 4n + 3 15 8 23 16 31 24 7 0 7 0 4n + 4 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address word data external data bus address chapter 5 bus control function user?s manual u16603ej5v1ud 212 (b) 8-bit data bus width (2/2) <3> access to address (4n + 2) first access second access third access fourth access word data external data bus address word data external data bus address word data external data bus address word data external data bus address 7 0 7 0 15 8 4n + 2 23 16 31 24 7 0 7 0 4n + 3 15 8 23 16 31 24 7 0 7 0 4n + 4 15 8 23 16 31 24 7 0 7 0 4n + 5 15 8 23 16 31 24 <4> access to address (4n + 3) first access second access third access fourth access 7 0 7 0 15 8 4n + 3 23 16 31 24 7 0 7 0 4n + 4 15 8 23 16 31 24 7 0 7 0 4n + 5 15 8 23 16 31 24 7 0 7 0 4n + 6 15 8 23 16 31 24 word data external data bus address word data external data bus address word data external data bus address word data external data bus address chapter 5 bus control function user?s manual u16603ej5v1ud 213 5.6 wait function 5.6.1 programmable wait function (1) data wait control register 0 (dwc0) to realize interfacing with a low-speed memory or i/o, up to seven data wait states can be inserted in the bus cycle that is executed for each cs space. the number of wait states can be pr ogrammed by using the dwc0 register . immediately after system reset, 7 data wait states are inserted for all the blocks. the dwc0 register can be read or written in 16-bit units. reset sets this register to 7777h. cautions 1. the internal rom and internal ram areas are not subject to programmable wait, and are always accessed without a wait state. the on-ch ip peripheral i/o area is also not subject to programmable wait, and only wait control from each peripheral function is performed. 2. write to the dwc0 register after reset, a nd then do not change the set values. also, do not access an external memory area until the in itial settings of the dwc0 register are complete. 3. when the v850es/sj2-h is used in separate bus mode and operated at f xx > 20 mhz, be sure to insert one or more wait. after reset: 7777h r/w address: fffff484h 0 0 dwc0 dw32 dw12 dw31 dw11 dw30 dw10 0 0 dw22 dw02 dw21 dw01 dw20 dw00 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 cs0 cs3 cs2 cs1 dwn2 0 0 0 0 1 1 1 1 dwn1 0 0 1 1 0 0 1 1 dwn0 0 1 0 1 0 1 0 1 none 1 2 3 4 5 6 7 none f xx 20 mhz f xx > 20 mhz setting prohibited multiplexed bus separate bus number of wait states inserted in csn space (n = 0 to 3) caution be sure to clear bits 15, 11, 7, and 3 to ?0?. chapter 5 bus control function user?s manual u16603ej5v1ud 214 5.6.2 external wait function to synchronize an extremely slow external memory, i/o, or asynchronous system, any number of wait states can be inserted in the bus cycle by using the external wait pin (wait). when the pcm0 pin is set to alternate function, the external wait function is enabled. access to each area of the internal rom, internal ram, a nd on-chip peripheral i/o is not subject to control by the external wait function, in the same man ner as the programmable wait function. the wait signal can be input asynchronously to clkout, and is sampled at the falling edge of the clock in the t2 and tw states of the bus cycle in the multiplexed bus mode. in the separate bus mode, it is sampled at the rising edge of the clock immediately after the t1 and tw states of the bus cycle. if the setup/hold time of the sampling timing is not satisfied, a wait state is inserted in the next state, or not inserted at all. chapter 5 bus control function user?s manual u16603ej5v1ud 215 5.6.3 relationship between programm able wait and external wait wait cycles are inserted as the result of an or operation between the wait cycles specifi ed by the set value of the programmable wait and the wait cycles controlled by the wait pin. wait control programmable wait wait via wait pin for example, if the timing of the programmable wait an d the wait pin signal is as illustrated below, three wait states will be inserted in the bus cycle. figure 5-3. inserting wait example (a) multiplexed bus clkout t1 t2 tw tw tw t3 wait pin wait via wait pin programmable wait wait control (b) separate bus t1 tw tw tw t2 clkout wait pin wait via wait pin programmable wait wait control remark the circles indicate the sampling timing. chapter 5 bus control function user?s manual u16603ej5v1ud 216 5.6.4 programmable address wait function address-setup or address-hold waits to be inserted in each bus cycle can be set by using the awc register. address wait insertion is set for each chip select area (cs0 to cs3). if an address setup wait is inserted, it seems that the high-clock period of the t1 state is extended by 1 clock. if an address hold wait is inserted, it seems that the low-cl ock period of the t1 state is extended by 1 clock. (1) address wait control register (awc) the awc register can be read or written in 16-bit units. reset sets this register to ffffh. cautions 1. address setup wait and address hold wa it cycles are not inserted when the internal rom area, internal ram area, and on-ch ip peripheral i/o areas are accessed. 2. write to the awc register after reset, a nd then do not change the set values. also, do not access an external memory area until the initial settings of the awc register are complete. 3. when the v850es/sj2-h is operated at f xx > 20 mhz, be sure to insert the address-hold wait and the address-setup wait. after reset: ffffh r/w address: fffff488h 1 ahw3 awc 1 asw3 1 ahw2 1 asw2 1 ahw1 1 asw1 1 ahw0 1 asw0 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 0 cs0 cs3 cs2 cs1 aswn 0 1 not inserted inserted setting prohibited inserted specifies insertion of address setup wait (n = 0 to 3) f xx 20 mhz f xx > 20 mhz ahwn 0 1 not inserted inserted setting prohibited inserted specifies insertion of address hold wait (n = 0 to 3) f xx 20 mhz f xx > 20 mhz caution be sure to set bits 15 to 8 to ?1?. chapter 5 bus control function user?s manual u16603ej5v1ud 217 5.7 idle state insertion function to facilitate interfacing with low-speed memories, one idle state (ti) can be inserted a fter the t3 state in the bus cycle that is executed for each space se lected by the chip select in the multiplex address/data bus mode. in the separate bus mode, one idle state (ti) can be inserted after the t2 state. by inserting an idle state, the data output float delay time of the memory can be secured during read access (an idle state cannot be inserted during write access). whether the idle state is to be inserted c an be programmed by using the bcc register. an idle state is inserted for all t he areas immediately after system reset. (1) bus cycle control register (bcc) the bcc register can be read or written in 16-bit units. reset sets this register to aaaah. cautions 1. the internal rom, internal ram, a nd on-chip peripheral i/o areas are not subject to idle state insertion. 2. write to the bcc register after reset, and then do not change the set values. also, do not access an external memory area until the initial settings of the bcc register are complete. after reset: aaaah r/w address: fffff48ah 1 bc31 bcn1 0 1 not inserted i nserted bcc 0 0 1 bc21 0 0 1 bc11 0 0 1 bc01 0 0 8 9 10 11 12 13 specifies insertion of idle state (n = 0 to 3) 14 15 1 2 3 4 5 6 7 0 cs0 cs3 cs2 cs1 caution be sure to set bits 15, 13, 11, and 9 to ?1?, and clear bits 14, 12, 10, 8, 6, 4, 2, and 0 to ?0?. chapter 5 bus control function user?s manual u16603ej5v1ud 218 5.8 bus hold function 5.8.1 functional outline the hldrq and hldak functions are valid if the pc m2 and pcm3 pins are set to alternate function. when the hldrq pin is asserted (low level), indicating th at another bus master has requested bus mastership, the external address/data bus goes into a high-impedance state and is released (bus hold status). if the request for the bus mastership is cleared and the hldrq pin is deasserted (high level), driving these pins is started again. during the bus hold period, execution of the program in the internal rom and internal ram is continued until an on-chip peripheral i/o register or t he external memory is accessed. the bus hold status is indicated by assertion of the hldak pin (low level). the bus hold function enables the configuration of mult i-processor type systems in which two or more bus masters exist. note that the bus hold request is not acknowledged during a multiple-acce ss cycle initiated by the bus sizing function or a bit manipulation instruction. status data bus width access type timing at which bus hold request is not acknowledged word access to even address between first and second access between first and second access word access to odd address between second and third access 16 bits halfword access to odd address between first and second access between first and second access between second and third access word access between third and fourth access cpu bus lock 8 bits halfword access between first and second access read-modify-write access of bit manipulation instruction ? ? between read access and write access chapter 5 bus control function user?s manual u16603ej5v1ud 219 5.8.2 bus hold procedure the bus hold status transition procedure is shown below. <1> hldrq = 0 acknowledged <2> all bus cycle start requests inhibited <3> end of current bus cycle <4> shift to bus idle status <5> hldak = 0 <6> hldrq = 1 acknowledged <7> hldak = 1 <8> bus cycle start request inhibition released <9> bus cycle starts normal status bus hold status normal status hldak (output) hldrq (input) <1> <2> <5> <3><4> <7><8><9> <6> 5.8.3 operation in power save mode because the internal system clock is stopped in the stop , idle1, and idle2 modes, the bus hold status is not entered even if the hldrq pin is asserted. in the halt mode, the hldak pin is asserted as soon as the hldrq pin has been asserted, and the bus hold status is entered. when the hldrq pin is later deassert ed, the hldak pin is also deasserted, and the bus hold status is cleared. chapter 5 bus control function user?s manual u16603ej5v1ud 220 5.9 bus priority bus hold, dma transfer, operand data accesses, instructio n fetch (branch), and instruction fetch (successive) are executed in the external bus cycle. bus hold has the highest priority, followed by dma trans fer, operand data access, instruction fetch (branch), and instruction fetch (successive). an instruction fetch may be inserted between the read access and write access in a read-modify-write access. if an instruction is executed for two or more accesses, an instruction fetch and bus hold are not inserted between accesses due to bus size limitations. table 5-4. bus priority priority external bus cycle bus master bus hold external device dma transfer dmac operand data access cpu instruction fetch (branch) cpu high low instruction fetch (successive) cpu chapter 5 bus control function user?s manual u16603ej5v1ud 221 5.10 bus timing figure 5-4. multiplexed bus read timing (bus size: 16 bits, 16-bit access) a1 a2 a3 d1 d2 a3 a2 a1 t1 t2 t3 t1 t2 tw tw t3 ti t1 programmable wait external wait idle state clkout a23 to a16 astb cs3 to cs0 wait ad15 to ad0 rd 8-bit access ad15 to ad8 ad7 to ad0 odd address active hi-z even address active hi-z remark the broken lines indicate high impedance. figure 5-5. multiplexed bus r ead timing (bus size: 8 bits) a1 a2 a3 d1 d2 a3 a2 a1 t1 t2 t3 t1 t2 tw tw t3 ti t1 programmable wait external wait idle state clkout a23 to a16, ad15 to ad8 astb cs3 to cs0 wait ad7 to ad0 rd remark the broken lines indicate high impedance. chapter 5 bus control function user?s manual u16603ej5v1ud 222 figure 5-6. multiplexed bus write timi ng (bus size: 16 bits, 16-bit access) a1 11 00 11 11 00 11 a2 a3 d1 d2 a3 a2 a1 t2 t3 t1 t1 t2 tw tw t3 t1 programmable wait external wait clkout a23 to a16 astb cs3 to cs0 wait ad15 to ad0 wr1, wr0 8-bit access ad15 to ad8 ad7 to ad0 wr1, wr0 odd address active undefined even address undefined 01 10 active figure 5-7. multiplexed bus wr ite timing (bus size: 8 bits) a1 11 10 11 11 10 11 a2 a3 d1 d2 a3 a2 a1 t2 t3 t1 t1 t2 tw tw t3 t1 programmable wait external wait clkout a23 to a16, ad15 to ad8 astb cs3 to cs0 wait ad7 to ad0 wr1, wr0 chapter 5 bus control function user?s manual u16603ej5v1ud 223 figure 5-8. multiplexed bus hold timing (bus si ze: 16 bits, 16-bit access) t1 a1 undefined a1 a2 t2 t3 th th th th ti note ti note t1 t2 t3 d1 clkout hldrq hldak a23 to a16 astb cs3 to cs0 ad15 to ad0 rd undefined undefined undefined a2 d2 1111 1111 note this idle state (ti) does not de pend on the bcc register settings. remarks 1. see table 2-2 for the pin statuses in the bus hold mode. 2. the broken lines indicate high impedance. chapter 5 bus control function user?s manual u16603ej5v1ud 224 figure 5-9. separate bus read timi ng (bus size: 16 bits, 16-bit access) t1 a1 a2 a3 t2 t1 tw tw t2 t2 ti t1 d3 d2 programmable wait external wait idle state d1 clkout a23 to a0 cs3 to cs0 wait ad15 to ad0 rd 8-bit access ad15 to ad8 ad7 to ad0 odd address active hi-z even address hi-z active remark the broken lines indicate high impedance. figure 5-10. separate bus r ead timing (bus size: 8 bits) t1 a1 a2 a3 t2 t1 tw tw t2 t2 ti t1 d3 d2 programmable wait external wait idle state d1 clkout a23 to a0 cs3 to cs0 wait ad7 to ad0 rd remark the broken lines indicate high impedance. chapter 5 bus control function user?s manual u16603ej5v1ud 225 figure 5-11. separate bus write timi ng (bus size: 16 bits, 16-bit access) t1 a1 11 00 00 00 11 11 11 11 a2 a3 t2 t1 tw tw t2 t1 t2 d3 d2 programmable wait external wait d1 clkout a23 to a0 cs3 to cs0 wait ad15 to ad0 wr1, wr0 8-bit access ad15 to ad8 ad7 to ad0 wr1, wr0 odd address active undefined even address undefined 01 10 active remark the broken lines indicate high impedance. figure 5-12. separate bus writ e timing (bus size: 8 bits) t1 a1 a2 a3 t2 t1 tw tw t2 t1 t2 d3 d2 programmable wait external wait d1 clkout a23 to a0 cs3 to cs0 wait ad7 to ad0 wr1, wr0 11 10 10 10 11 11 11 11 remark the broken lines indicate high impedance. chapter 5 bus control function user?s manual u16603ej5v1ud 226 figure 5-13. separate bus hold ti ming (bus size: 8 bits, write) clkout t1 t2 a1 d1 d2 undefined a2 undefined 11 11 10 d3 a3 t1 t2 th ti note ti note th th th t1 t2 hldrq hldak a23 to a0 ad7 to ad0 wr1, wr0 cs3 to cs0 11 10 11 10 1111 1111 11 note this idle state (ti) does not de pend on the bcc register settings. remark the broken lines indicate high impedance. figure 5-14. address wait timing (separate bus read, bus size: 16 bits, 16-bit access) tasw t1 tahw t2 clkout astb a23 to a0 cs3 to cs0 wait ad15 to ad0 rd d1 a1 t1 t2 clkout astb a23 to a0 cs3 to cs0 wait ad15 to ad0 rd d1 a1 remarks 1. tasw (address setup wait): image of hi gh-level width of t1 state expanded. 2. tahw (address hold wait): image of lo w-level width of t1 state expanded. 3. the broken lines indicate high impedance. user?s manual u16603ej5v1ud 227 chapter 6 clock generation function 6.1 overview the following clock generation functions are available. { main clock oscillator ? in clock-through mode v850es/sj2: f x = 2.5 to 10 mhz (f xx = 2.5 to 10 mhz) v850es/sj2-h: f x = 2.5 to 8 mhz (f xx = 2.5 to 8 mhz) ? in pll mode v850es/sj2: f x = 2.5 to 5 mhz (f xx = 10 to 20 mhz) v850es/sj2-h: f x = 2.5 to 5 mhz ( 4: f xx = 10 to 20 mhz) f x = 2.5 to 4 mhz ( 8: f xx = 20 to 32 mhz) { subclock oscillator ? f xt = 32.768 khz { multiply ( 4/ 8) function by pll (phase locked loop) ? clock-through mode/pll mode selectable { internal oscillator ? f r = 200 khz (typ.) { internal system clock generation ? 7 steps (f xx , f xx /2, f xx /4, f xx /8, f xx /16, f xx /32, f xt ) { peripheral clock generation { clock output function remark f x : main clock oscillation frequency f xx : main clock frequency f xt : subclock frequency f r : internal oscillation clock frequency chapter 6 clock generation function user?s manual u16603ej5v1ud 228 6.2 configuration figure 6-1. clock generator selector selector note frc bit mfrc bit mck bit ck2 to ck0 bits selpll bit pllon bit cls, ck3 bits stop mode subclock oscillator port cm prescaler 1 prescaler 2 idle control halt control halt mode cpu clock watch timer clock timer m clock watch timer clock, watchdog timer 2 clock peripheral clock, watchdog timer 2 clock watchdog timer 2 clock, timer m clock internal system clock prescaler 3 main clock oscillator main clock oscillator stop control rstop bit internal oscillator 1/8 divider xt1 xt2 clkout x1 x2 idle mode pll f xx /32 f xx /16 f xx /8 f xx /4 f xx /2 f xx f cpu f clk f xx to f xx /1,024 can controller f can f brg = f x /2 to f x /2 12 f xt f xt f xx f x f r f r /8 idle control selector selector note the internal oscillation clock is selected when t he watchdog timer 2 overflows during the oscillation stabilization time. remark f x : main clock oscillation frequency f xx : main clock frequency f clk : internal system clock frequency f xt : subclock frequency f cpu : cpu clock frequency f brg : watch timer clock frequency f r : internal oscillation clock frequency f can : can clock frequency chapter 6 clock generation function user?s manual u16603ej5v1ud 229 (1) main clock oscillator the main resonator oscillates the following frequencies (f x ). ? in clock-through mode v850es/sj2: f x = 2.5 to 10 mhz v850es/sj2-h: f x = 2.5 to 8 mhz ? in pll mode v850es/sj2: f x = 2.5 to 5 mhz v850es/sj2-h: f x = 2.5 to 5 mhz ( 4) f x = 2.5 to 4 mhz ( 8) (2) subclock oscillator the sub-resonator oscillates a frequency of 32.768 khz (f xt ). (3) main clock oscillator stop control this circuit generates a control signal that stops oscillation of the main clock oscillator. oscillation of the main clock oscillat or is stopped in the stop mode or when the pcc.mck bit = 1 (valid only when the pcc.cls bit = 1). (4) internal oscillator oscillates a frequency (f r ) of 200 khz (typ.). (5) prescaler 1 this prescaler generates the clock (f xx to f xx /1,024) to be supplied to the following on-chip peripheral functions: tmp0 to tmp8, tmq0, tmm0, csib0 to csib5, uarta0 to uarta3, i 2 c00 to i 2 c02 note 1 , adc, wdt2, can0 note 2 , can1 note 3 , and iebus note 4 notes 1. i 2 c bus versions (y products) only 2. can controller versions only 3. can controller (2-channel) versions only 4. iebus versions only (6) prescaler 2 this circuit divides the main clock (f xx ). the clock generated by prescaler 2 (f xx to f xx /32) is supplied to the selector that generates the cpu clock (f cpu ) and internal system clock (f clk ). f clk is the clock supplied to the intc, rom correction, rom, and ram blocks, and can be output from the clkout pin. (7) prescaler 3 this circuit divides the clock generated by the main clock oscillator (f x ) to a specific frequency (32.768 khz) and supplies that clock to the watch timer block. for details, see chapter 10 watch timer functions . (8) pll this circuit multiplies the clock generated by the main clock oscillator (f x ) by 4 or 8. it operates in two modes: clock-through mode in which f x is output as is, and pll mode in which a multiplied clock is output. these modes can be sele cted by using the pllctl.selpll bit. whether the clock is multiplied by 4 or 8 is selected by the ckc.ckdiv0 bit, and pll is started or stopped by the pllctl.pllon bit. chapter 6 clock generation function user?s manual u16603ej5v1ud 230 6.3 registers (1) processor clock control register (pcc) the pcc register is a special register. data can be wr itten to this register only in combination of specific sequences (see 3.4.8 special registers ). this register can be read or written in 8-bit or 1-bit units. reset input sets this register to 03h. chapter 6 clock generation function user?s manual u16603ej5v1ud 231 frc used not used frc 0 1 use of subclock on-chip feedback resistor pcc mck mfrc cls note ck3 ck2 ck1 ck0 oscillation enabled oscillation stopped mck 0 1 main clock oscillator control used not used mfrc 0 1 use of main clock on-chip feedback resistor after reset: 03h r/w address: fffff828h main clock operation subclock operation cls note 0 1 status of cpu clock (f cpu ) < > < > < > f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 setting prohibited f xt ck2 0 0 0 0 1 1 1 clock selection (f clk /f cpu ) ck1 0 0 1 1 0 0 1 ck0 0 1 0 1 0 1 ck3 0 0 0 0 0 0 0 1 even if the mck bit is set (1) while the system is operating with the main clock as the cpu clock, the operation of the main clock does not stop. it stops after the cpu clock has been changed to the subclock. before setting the mck bit from 0 to 1, stop the on-chip peripheral functions operating with the main clock. when the main clock is stopped and the device is operating with the subclock, clear (0) the mck bit and secure the oscillation stabilization time by software before switching the cpu clock to the main clock or operating the on-chip peripheral functions. ? ? ? note the cls bit is a read-only bit. cautions 1. do not change the cpu clock (by using the ck3 to ck0 bits) while clkout is being output. 2. use a bit manipulation instruction to ma nipulate the ck3 bit. when using an 8-bit manipulation instruction, do not change the set values of the ck2 to ck0 bits. remark : don?t care chapter 6 clock generation function user?s manual u16603ej5v1ud 232 (a) example of setting main clock operation subclock operation <1> ck3 bit 1: use of a bit manipulation instructi on is recommended. do not change the ck2 to ck0 bits. <2> subclock operation: read the cls bit to check if subclock operation has started. it takes the following time after the ck3 bit is se t until subclock operation is started. max.: 1/f xt (1/subclock frequency) <3> mck bit 1: set the mck bit to 1 only when stopping the main clock. cautions 1. when stopping the ma in clock, stop the pll. also stop the operations of the on-chip peripheral functions operati ng with the main clock. 2. if the following conditions are not satisfi ed, change the ck2 to ck0 bits so that the conditions are satisfied, then change to the subclock operation mode. internal system clock (f clk ) > subclock (f xt : 32.768 khz) 4 remark internal system clock (f clk ): clock generated from the main clock (f xx ) by setting bits ck2 to ck0 [description example] _dma_disable: clrl 0, dchcn[r0] -- dma operation disabled. n = 0 to 3 <1> _set_sub_run : st.b r0, prcmd[r0] set1 3, pcc[r0] -- ck3 bit 1 <2> _check_cls : tst1 4, pcc[r0] -- wait until subclock operation starts. bz _check_cls <3> _stop_main_clock : st.b r0, prcmd[r0] set1 6, pcc[r0] -- mck bit 1, main clock is stopped. _dma_enable: setl 0, dchcn[r0] -- dma operation enabled. n = 0 to 3 remark the description above is simply an example. no te that in <2> above, the cls bit is read in a closed loop. chapter 6 clock generation function user?s manual u16603ej5v1ud 233 (b) example of setting subclock operation main clock operation <1> mck bit 0: main clock starts oscillating <2> insert waits by the program and wait until the oscillation stabilizat ion time of the main clock elapses. <3> ck3 bit 0: use of a bit manipulation instruction is recommended. do not change the ck2 to ck0 bits. <4> main clock operation: it takes the following time after the ck3 bit is set until main clock operation is started. max.: 1/f xt (1/subclock frequency) therefore, insert one nop instructi on immediately after setting the ck3 bit to 0 or read the cls bit to check if main clock operation has started. caution enable operation of the on-chip peripher al functions operating with the main clock only after the oscillation of the main clock stabilizes. if their operations are enabled before the lapse of the oscillation stabilizat ion time, a malfunction may occur. [description example] _dma_disable: clrl 0, dchcn[r0] -- dma operation disabled. n = 0 to 3 <1> _start_main_osc : st.b r0, prcmd[r0] -- release of protection of special registers clr1 6, pcc[r0] -- main clock starts oscillating. <2> movea 0x55, r0, r11 -- wait for oscillation stabilization time. _wait_ost : nop nop nop addi -1, r11, r11 cmp r0, r11 bne _wait_ost <3> st.b r0, prcmd[r0] clr1 3, pcc[r0] -- ck3 0 <4> _check_cls : tst1 4, pcc[r0] -- wait until main clock operation starts. bnz _check_cls _dma_enable: setl 0, dchcn[r0] -- dma operation enabled. n = 0 to 3 remark the description above is simply an example. no te that in <4> above, the cls bit is read in a closed loop. chapter 6 clock generation function user?s manual u16603ej5v1ud 234 (2) internal oscillati on mode register (rcm) the rcm register is an 8-bit register that sets the operation mode of the internal oscillator. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 rcm 0 0 0 00 0 rstop internal oscillator oscillating internal oscillator stopped rstop 0 1 oscillation/stop of internal oscillator after reset: 00h r/w address: fffff80ch < > cautions 1. the internal osc illator cannot be stopped while the cpu is operating on the internal oscillation clock (ccls.cclsf bit = 1). do not set the rstop bit to 1. 2. the internal oscillator oscillates if the ccls.cclsf bit is set to 1 (when wdt overflow occurs during oscillation stabilization) even wh en the rstop bit is set to 1. at this time, the rstop bit rema ins being set to 1. (3) cpu operation clock status register (ccls) the ccls register indicates the stat us of the cpu operation clock. this register is read-only, in 8-bit or 1-bit units. reset sets this register to 00h. 0 ccls 0 0 0 0 0 0 cclsf after reset: 00h note r address: fffff82eh operating on main clock (f x ) or subclock (f xt ). operating on internal oscillation clock (f r ). cclsf 0 1 cpu operation clock status note if wdt overflow occurs during oscillation stabilizati on after a reset is released, the cpu operates on the internal oscillation clock (f r ). at this time, the cclsf bit is set to 1 and the reset value is 01h. chapter 6 clock generation function user?s manual u16603ej5v1ud 235 6.4 operation 6.4.1 operation of each clock the following table shows the oper ation status of each clock. table 6-1. operation status of each clock pcc register clk bit = 0, mck bit = 0 cls bit = 1, mck bit = 0 cls bit = 1, mck bit = 1 register setting and operation status target clock during reset during oscillation stabilization time count halt mode idle1, idle2 mode stop mode subclock mode sub-idle mode subclock mode sub-idle mode main clock oscillator (f x ) subclock oscillator (f xt ) cpu clock (f cpu ) internal system clock (f clk ) main clock (in pll mode, f xx ) note peripheral clock (f xx to f xx /1,024) wt clock (main) wt clock (sub) wdt2 clock (internal oscillation) wdt2 clock (main) wdt2 clock (sub) note lockup time remark : operable : stopped 6.4.2 clock output function the clock output function is used to output the internal system clock (f clk ) from the clkout pin. the internal system clock (f clk ) is selected by using the pcc.ck3 to pcc.ck0 bits. the clkout pin functions alte rnately as the pcm1 pin and functions as a clock output pin if so specified by the control register of port cm. the status of the clko ut pin is the same as the in ternal system clock in table 6-1 and the pin can output the clock when it is in the operable status. it outputs a low level in the stopped stat us. however, the clkout pin is in the port mode (pcm1 pin: input mode) after reset and until it is set in the output mode. ther efore, the stat us of the pin is hi-z. chapter 6 clock generation function user?s manual u16603ej5v1ud 236 6.5 pll function 6.5.1 overview in the v850es/sj2 and v850es/sj2-h, an oper ating clock that is 4 or 8 times hi gher than the oscillation frequency output by the pll function or the clock-through mode can be selected as the operating clock of the cpu and on-chip peripheral functions. ? v850es/sj2 when pll function is used: input clock = 2.5 to 5 mhz (output: 10 to 20 mhz) clock-through mode: input clock = 2.5 to 10 mhz (output: 2.5 to 10 mhz) ? v850es/sj2-h when pll function is used ( 4): input clock = 2.5 to 5 mhz (output: 10 to 20 mhz) when pll function is used ( 8): input clock = 2.5 to 4 mhz (output: 20 to 32 mhz) clock-through mode: input clock = 2.5 to 8 mhz (output: 2.5 to 8 mhz) 6.5.2 registers (1) pll control register (pllctl) the pllctl register is an 8-bit regi ster that controls the pll function. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 01h. 0 pllctl 0 0 0 00 selpll pllon pll stopped pll operating (after pll operation starts, a lockup time is required for frequency stabilization) pllon 0 1 pll operation stop register clock-through mode pll mode selpll 0 1 cpu operation clock selection register after reset: 01h r/w address: fffff82ch < > < > cautions 1. to stop the pll operation, first set th e clock through mode (selpll bit = 0), wait for at least 8 clocks, and then stop the pll (pllon bit = 0). when the pllon bit is cleared to 0, the selpll bit is automatically cleared to 0 (clock-through mode), but be sure to stop the pll in the above procedure. 2. the selpll bit can be set to 1 only when the pll clock frequency is stabilized. if not (unlocked), ?0? is written to the sel pll bit if data is written to it. chapter 6 clock generation function user?s manual u16603ej5v1ud 237 (2) clock control register (ckc) the ckc register is a special register. data can be wri tten to this register only in a combination of specific sequence (see 3.4.8 special registers ). the ckc register controls the inte rnal system clock in the pll mode. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 0ah. 0 ckc 0 0 0 1 0 1 ckdiv0 after reset: 0ah r/w address: fffff822h f xx = 4 f x (f x = 2.5 to 5.0 mhz) ckdiv0 0 1 internal system clock (f xx ) in pll mode v850es/sj2: f xx = 8 f x (f x = 2.5 mhz) v850es/sj2-h: f xx = 8 f x (f x = 2.5 to 4.0 mhz) cautions 1. the pll mode cannot be used in case of the following oscillation frequency. ? v850es/sj2: 5.0 mhz < f x 10.0 mhz ? v850es/sj2-h: 5.0 mhz < f x 8.0 mhz 2. before changing the mult iplication factor between 4 a nd 8 by using the ckc register, set the clock-through mode and stop the pll. 3. be sure to set bits 3 and 1 to ?1 ? and clear bits 7 to 4 and 2 to ?0?. remark both the cpu clock and peripheral clock are divided by the ckc register, but only the cpu clock is divided by the pcc register. chapter 6 clock generation function user?s manual u16603ej5v1ud 238 (3) lock register (lockr) phase lock occurs at a given frequency following powe r application or immediately after the stop mode is released, and the time required for stabilization is the lockup time (frequency stabilization time). this state until stabilization is called the lock up status, and the stabilized state is called the locked status. the lockr register includes a lock bit that re flects the pll frequency stabilization status. this register is read-only, in 8-bit or 1-bit units. reset sets this register to 00h. 0 lockr 0 0 0 00 0 lock locked status unlocked status lock 0 1 pll lock status check after reset: 00h r address: fffff824h < > caution the lock register does not reflect the lock status of the p ll in real time. the set/clear conditions are as follows. [set conditions] ? upon system reset note ? in idle2 or stop mode ? upon setting of pll stop (clearing of pllctl.pllon bit to 0) ? upon stopping main clock and using cpu with subclock (setting of pcc.ck3 bit to 1 and setting of pcc.mck bit to 1) note this register is set to 01h by reset and cleared to 00h after the reset has been released and the oscillation stabilization time has elapsed. [clear conditions] ? upon overflow of oscillation stabilization time fo llowing reset release (osts register default time (see 24.2 (3) oscillation stabilization time select register (osts) )) ? upon oscillation stabilization timer overflow (time set by osts register) following stop mode release, when the stop mode was set in the pll operating status ? upon pll lockup time timer overflow (time set by plls register) when the pllctl.pllon bit is changed from 0 to 1 ? after the setup time inserted upon release of the idle2 mode is released (time set by the osts register) when the idle2 mode is set during pll operation. chapter 6 clock generation function user?s manual u16603ej5v1ud 239 (4) pll lockup time specification register (plls) the plls register is an 8-bit register used to sele ct the pll lockup time when the pllctl.pllon bit is changed from 0 to 1. this register can be read or written in 8-bit units. reset sets this register to 03h. 0 2 10 /f x 2 11 f x 2 12 /f x 2 13 /f x (default value) plls1 0 0 1 1 plls0 0 1 0 1 selection of pll lockup time plls 0 0 0 0 0 plls1 plls0 after reset: 03h r/w address: fffff6c1h cautions 1. set so that the lockup time is 800 s or longer. 2. do not change the plls regi ster setting during the lockup period. 6.5.3 usage (1) when pll is used ? after the reset signal has been released, the pll operates (pllctl.pllon bit = 1), but because the default mode is the clock-through mode (pllctl.selpll bi t = 0), select the pll mode (selpll bit = 1). ? to enable pll operation, first set the pllon bit to 1, and then set the selpll bit to 1 after the lockr.lock bit = 0. to stop the pll, first select the clock-through mode (selpll bit = 0), wait for 8 clocks or more, and then stop the pll (pllon bit = 0). ? the pll stops during transition to idle2 or stop m ode regardless of the setting and is restored from idle2 or stop mode to the status before transition. the time requir ed for restoration is as follows. (a) to set the idle2/stop mode in clock through mode ? stop mode: set the osts register so that the o scillation stabilization time is 1 ms (min.) or more. ? idle2 mode: set the osts register so that the setup time is 350 s (min.) or more. (b) to set idle2/stop mode in pll operation mode ? stop mode: set the osts register so that the o scillation stabilization time is 1 ms (min.) or more. ? idle2 mode: set the osts register so that the setup time is 800 s (min.) or more. when shifting to the idle1 mode, the pll d oes not stop. stop the pll if necessary. (2) when pll is not used ? the clock-through mode (selpll bit = 0) is selected a fter the reset signal has been released, but the pll is operating (pllon bit = 1) and must t herefore be stopped (pllon bit = 0). user?s manual u16603ej5v1ud 240 chapter 7 16-bit timer/event counter p (tmp) timer p (tmp) is a 16-bit timer/event counter. the v850es/sj2 and v850es/sj2-h have six timer/event counter channels, tmp0 to tmp8. 7.1 overview an outline of tmpn is shown below. ? clock selection: 8 ways ? capture/trigger input pins: 2 ? external event count input pins: 1 ? external trigger input pins: 1 ? timer/counters: 1 ? capture/compare registers: 2 ? capture/compare match interrupt request signals: 2 ? overflow interrupt request signals: 1 ? timer output pins: 2 remark n = 0 to 8 7.2 functions tmpn has the following functions. ? interval timer ? external event counter ? external trigger pulse output ? one-shot pulse output ? pwm output ? free-running timer ? pulse width measurement remark n = 0 to 8 chapter 7 16-bit timer/event counter p (tmp) user?s manual u16603ej5v1ud 241 7.3 configuration tmpn includes the following hardware. table 7-1. configuration of tmpn item configuration timer register 16-bit counter registers tmpn capture/compare registers 0, 1 (tpnccr0, tpnccr1) tmpn counter read buffer register (tpncnt) ccr0, ccr1 buffer registers timer inputs 2 (tipn0 note 1 , tipn1 pins) timer outputs 2 (topn0, topn1 pins) control registers note 2 tmpn control registers 0, 1 (tpnctl0, tpnctl1) tmpn i/o control registers 0 to 2 (tpnioc0 to tpnioc2) tmpn option register 0 (tpnopt0) notes 1. the tipn0 pin functions alternately as a capture trigger input signal, external event count input signal, and external trigger input signal. 2. when using the functions of the tipn0, tipn1, topn0, and topn1 pins, see table 4-19 using port pin as alternate-function pin . remark n = 0 to 8 figure 7-1. block diagram of tmpn f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 note 1 , f xx /256 note 2 f xx /128 note 1 , f xx /512 note 2 selector internal bus internal bus topn0 topn1 tipn0 tipn1 selector edge detector ccr0 buffer register ccr1 buffer register tpnccr0 tpnccr1 16-bit counter tpncnt inttpnov inttpncc0 inttpncc1 output controller clear notes 1. tmp0, tmp2, tmp4, tmp6, tmp8 2. tmp1, tmp3, tmp5, tmp7 remark f xx : main clock frequency chapter 7 16-bit timer/event counter p (tmp) user?s manual u16603ej5v1ud 242 (1) 16-bit counter this 16-bit counter can count inte rnal clocks or external events. the count value of this counter can be read by using the tpncnt register. when the tpnctl0.tpnce bit = 0, the va lue of the 16-bit counter is ffffh. if the tpncnt register is read at this time, 0000h is read. reset sets the tpnce bit to 0. (2) ccr0 buffer register this is a 16-bit compare register that com pares the count value of the 16-bit counter. when the tpnccr0 register is used as a compare regist er, the value written to the tpnccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the value of the ccr0 buffer register, a compare match interrupt request signal (inttpncc0) is generated. the ccr0 buffer register cannot be read or written directly. the ccr0 buffer register is cleared to 0000h after reset, as the tpnccr0 register is cleared to 0000h. (3) ccr1 buffer register this is a 16-bit compare register that com pares the count value of the 16-bit counter. when the tpnccr1 register is used as a compare regist er, the value written to the tpnccr1 register is transferred to the ccr1 buffer register. when the count value of the 16-bit counter matches the value of the ccr1 buffer register, a compare match interrupt request signal (inttpncc1) is generated. the ccr1 buffer register cannot be read or written directly. the ccr1 buffer register is cleared to 0000h after reset, as the tpnccr1 register is cleared to 0000h. (4) edge detector this circuit detects the valid edges input to the tipn0 and tipn1 pins. no edge, rising edge, falling edge, or both the rising and falling edges can be selected as the valid edge by using the tpnioc1 and tpnioc2 registers. (5) output controller this circuit controls the output of the topn0 and topn 1 pins. the output contro ller is controlled by the tpnioc0 register. (6) selector this selector selects the count clock for the 16-bit counter . eight types of internal clocks or an external event can be selected as the count clock. chapter 7 16-bit timer/event counter p (tmp) user?s manual u16603ej5v1ud 243 7.4 registers the registers that control tmpn are as follows. ? tmpn control register 0 (tpnctl0) ? tmpn control register 1 (tpnctl1) ? tmpn i/o control register 0 (tpnioc0) ? tmpn i/o control register 1 (tpnioc1) ? tmpn i/o control register 2 (tpnioc2) ? tmpn option register 0 (tpnopt0) ? tmpn capture/compare register 0 (tpnccr0) ? tmpn capture/compare register 1 (tpnccr1) ? tmpn counter read buffer register (tpncnt) remarks 1. when using the functions of the tipn0, tipn1,to pn0, and topn1 pins, see table 4-19 using port pin as alternate-function pin . 2. n = 0 to 8 chapter 7 16-bit timer/event counter p (tmp) user?s manual u16603ej5v1ud 244 (1) tmpn control register 0 (tpnctl0) the tpnctl0 register is an 8-bit register that controls the operation of tmpn. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. the same value can always be written to the tpnctl0 register by software. tpnce tmpn operation disabled (tmpn reset asynchronously note ). tmpn operation enabled. tmpn operation started. tpnce 0 1 tmpn operation control tpnctl0 (n = 0 to 8) 0 0 0 0 tpncks2 tpncks1 tpncks0 654321 after reset: 00h r/w address: tp0ctl0 fffff590h, tp1ctl0 fffff5a0h, tp2ctl0 fffff5b0h, tp3ctl0 fffff5c0h, tp4ctl0 fffff5d0h, tp5ctl0 fffff5e0h, tp6ctl0 fffff5f0h, tp7ctl0 fffff600h, tp8ctl0 fffff610h <7> 0 f xx f xx /2 f xx /4 f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 f xx /256 f xx /512 tpncks2 0 0 0 0 1 1 1 1 internal count clock selection n = 0, 2, 4, 6, 8 n = 1, 3, 5, 7 tpncks1 0 0 1 1 0 0 1 1 tpncks0 0 1 0 1 0 1 0 1 note the tpnopt0.tpnovf bit and 16-bit counter are re set at the same time. in addition, the timer output pins (topn0 and topn1 pins) are reset to t he status set by the tpnioc0 register when the 16-bit counter is reset. cautions 1. set the tpncks2 to tpncks0 bits when the tpnce bit = 0. when the value of the tpnce bit is change d from 0 to 1, the tpncks2 to tpncks0 bits can be set simultaneously. 2. be sure to clear bits 3 to 6 to ?0?. remark f xx : main clock frequency (2) tmpn control register 1 (tpnctl1) the tpnctl1 register is an 8-bit register that controls the operation of tmpn. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. chapter 7 16-bit timer/event counter p (tmp) user?s manual u16603ej5v1ud 245 0 tpnest 0 1 software trigger control tpnctl1 (n = 0 to 8) tpnest tpneee 0 0 tpnmd2 tpnmd1 tpnmd0 <6> <5> 4 3 2 1 after reset: 00h r/w address: tp0ctl1 fffff591h, tp1ctl1 fffff5a1h, tp2ctl1 fffff5b1h, tp3ctl1 fffff5c1h, tp4ctl1 fffff5d1h, tp5ctl1 fffff5e1h, tp6ctl1 fffff5f1h, tp7ctl1 fffff601h, tp8ctl1 fffff611h generate a valid signal for external trigger input. ? in one-shot pulse output mode: a one-shot pulse is output with writing 1 to the tpnest bit as the trigger. ? in external trigger pulse output mode: a pwm waveform is output with writing 1 to the tpnest bit as the trigger. disable operation with external event count input (tipn0 pin). (perform counting with the count clock selected by the tpnctl0.tpncks0 to tpncks2 bits.) tpneee 0 1 count clock selection the tpneee bit selects whether counting is performed with the internal count clock or the valid edge of the external event count input. 7 0 interval timer mode external event count mode external trigger pulse output mode one-shot pulse output mode pwm output mode free-running timer mode pulse width measurement mode setting prohibited tpnmd2 0 0 0 0 1 1 1 1 timer mode selection tpnmd1 0 0 1 1 0 0 1 1 tpnmd0 0 1 0 1 0 1 0 1 enable operation with external event count input (tipn0 pin). (perform counting at the valid edge of the external event count input signal (tipn0 pin).) ? the read value of the tpnest bit is always 0. cautions 1. the tpnest bit is valid only in the external trigger pulse output mode or the one-shot pulse output mode. in any other mode, writing 1 to this bit is ignored. 2. external event count input is selected in the external event count mode regardless of the value of the tpneee bit. 3. set the tpneee and tpnmd2 to tpnmd0 bits when the tpnctl0.tpnce bit = 0. (the same value can be written when the tpnce bi t = 1.) the operation is not guaranteed when rewriting is performed with the tpnc e bit = 1. if rewriting was mistakenly performed, clear the tpnce bit to 0 and then set the bits again. 4. be sure to clear bits 3, 4, and 7 to ?0?. chapter 7 16-bit timer/event counter p (tmp) user?s manual u16603ej5v1ud 246 (3) tmpn i/o control register 0 (tpnioc0) the tpnioc0 register is an 8-bit register that controls the timer output (topn0, topn1 pins). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. chapter 7 16-bit timer/event counter p (tmp) user?s manual u16603ej5v1ud 247 0 tpnol1 0 1 topn1 pin output level setting note topn1 pin high level start topn1 pin low level start tpnioc0 (n = 0 to 8) 0 0 0 tpnol1 tpnoe1 tpnol0 tpnoe0 6543<2>1 after reset: 00h r/w address: tp0ioc0 fffff592h, tp1ioc0 fffff5a2h, tp2ioc0 fffff5b2h, tp3ioc0 fffff5c2h, tp4ioc0 fffff5d2h, tp5ioc0 fffff5e2h, tp6ioc0 fffff5f2h, tp7ioc0 fffff602h, tp8ioc0 fffff612h tpnoe1 0 1 topn1 pin output setting timer output disabled ? when tpnol1 bit = 0: low level is output from the topn1 pin ? when tpnol1 bit = 1: high level is output from the topn1 pin tpnol0 0 1 topn0 pin output level setting note topn0 pin high level start topn0 pin low level start tpnoe0 0 1 topn0 pin output setting timer output disabled ? when tpnol0 bit = 0: low level is output from the topn0 pin ? when tpnol0 bit = 1: high level is output from the topn0 pin 7 <0> timer output enabled (a pulse is output from the topn1 pin). timer output enabled (a pulse is output from the topn0 pin). note the output level of the timer out put pins (topn0, topn1) specifie d by the tpnolm bit is shown below (m = 0, 1). tpnce bit topnm pin output 16-bit counter ? when tpnolm bit = 0 tpnce bit topnm pin output 16-bit counter ? when tpnolm bit = 1 cautions 1. the pin output changes if the setting of the tpnioc0 register is rewritten when the port is set to output topn0 and topn1. therefore, note changes in the pin status by setting the port to the input mode and making the output status of the pins a high-impedance state. 2. rewrite the tpnol1, tpnoe1, tpnol0, a nd tpnoe0 bits when the tpnctl0.tpnce bit = 0. (the same value can be written when the tpnce bit = 1.) if rewriting was mistakenly performed, clear the tpnce bi t to 0 and then set the bits again. 3. even if the tpnolm bit is manipulated when the tpnce and tpnoem bits are 0, the topnm pin output level varies (m = 0, 1). chapter 7 16-bit timer/event counter p (tmp) user?s manual u16603ej5v1ud 248 (4) tmpn i/o control register 1 (tpnioc1) the tpnioc1 register is an 8-bit regist er that controls the valid edge of the capture trig ger input signals (tipn0, tipn1 pins). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 tpnis3 0 0 1 1 tpnis2 0 1 0 1 capture trigger input signal (tipn1 pin) valid edge setting no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges tpnioc1 (n = 0 to 8) 0 0 0 tpnis3 tpnis2 tpnis1 tpnis0 654321 after reset: 00h r/w address: tp0ioc1 fffff593h, tp1ioc1 fffff5a3h, tp2ioc1 fffff5b3h, tp3ioc1 fffff5c3h, tp4ioc1 fffff5d3h, tp5ioc1 fffff5e3h, tp6ioc1 fffff5f3h, tp7ioc1 fffff603h, tp8ioc1 fffff613h tpnis1 0 0 1 1 tpnis0 0 1 0 1 capture trigger input signal (tipn0 pin) valid edge setting no edge detection (capture operation invalid) detection of rising edge detection of falling edge detection of both edges 7 0 cautions 1. rewrite the tpnis3 to tpnis0 bits when the tpnctl0.tpnce bit = 0. (the same value can be written when the tpnce bit = 1.) if rewriting was mistakenly performed, clear the tpnce bit to 0 and then set the bits again. 2. the tpnis3 to tpnis0 bits are valid only in the free-running timer mode (only when tpnopt0.tpnccs1, tpnccs0 bits = 11) and the pulse width measurement mode. in all other modes, a capture operation is not possible. chapter 7 16-bit timer/event counter p (tmp) user?s manual u16603ej5v1ud 249 (5) tmpn i/o control register 2 (tpnioc2) the tpnioc2 register is an 8-bit register that controls the valid edge of the external event count input signal (tipn0 pin) and external trigger input signal (tipn0 pin). this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 tpnees1 0 0 1 1 tpnees0 0 1 0 1 external event count input signal (tipn0 pin) valid edge setting no edge detection (external event count invalid) detection of rising edge detection of falling edge detection of both edges tpnioc2 (n = 0 to 8) 0 0 0 tpnees1 tpnees0 tpnets1 tpnets0 654321 after reset: 00h r/w address: tp0ioc2 fffff594h, tp1ioc2 fffff5a4h, tp2ioc2 fffff5b4h, tp3ioc2 fffff5c4h, tp4ioc2 fffff5d4h, tp5ioc2 fffff5e4h, tp6ioc2 fffff5f4h, tp7ioc2 fffff604h, tp8ioc2 fffff614h tpnets1 0 0 1 1 tpnets0 0 1 0 1 external trigger input signal (tipn0 pin) valid edge setting no edge detection (external trigger invalid) detection of rising edge detection of falling edge detection of both edges 7 0 cautions 1. rewrite the tpnees1, tpnees0, tpnets1, and tpnets0 bits when the tpnctl0.tpnce bit = 0. (the same value can be written wh en the tpnce bit = 1.) if rewriting was mistakenly performed, clear the tpnce bit to 0 and then set the bits again. 2. the tpnees1 and tpnees0 bits are valid only when the tpnctl1.tpneee bit = 1 or when the external event count mode (t pnctl1.tpnmd2 to tpnctl1.tpnmd0 bits = 001) has been set. 3. the tpnets1 and tpnets0 bits are valid only when the external trigger pulse output mode (tpnctl1.tpnmd2 to tp nctl1.tpnmd0 bits = 010) or the one-shot pulse output mode (tpnctl1.tpnmd2 to tpnctl1.tpnmd0 = 011) is set. chapter 7 16-bit timer/event counter p (tmp) user?s manual u16603ej5v1ud 250 (6) tmpn option register 0 (tpnopt0) the tpnopt0 register is an 8-bit register used to set the capture/compare operation and detect an overflow. this register can be read or written in 8-bit or 1-bit units. reset sets this register to 00h. 0 tpnccs1 0 1 tpnccr1 register capture/compare selection the tpnccs1 bit setting is valid only in the free-running timer mode. compare register selected capture register selected (cleared by setting tpnctl0.tpnce bit = 0) tpnopt0 (n = 0 to 8) 0 tpnccs1 tpnccs0 0 0 0 tpnovf 654321 after reset: 00h r/w address: tp0opt0 fffff595h, tp1opt0 fffff5a5h, tp2opt0 fffff5b5h, tp3opt0 fffff5c5h, tp4opt0 fffff5d5h, tp5opt0 fffff5e5h, tp6opt0 fffff5f5h, tp7opt0 fffff605h, tp8opt0 fffff615h tpnccs0 0 1 tpnccr0 register capture/compare selection the tpnccs0 bit setting is valid only in the free-running timer mode. compare register selected capture register selected (cleared by setting tpnctl0.tpnce bit = 0) tpnovf set (1) reset (0) tmpn overflow detection flag ? the tpnovf bit is set to 1 when the 16-bit counter count value overflows from ffffh to 0000h in the free-running timer mode or the pulse width measurement mode. ? an overflow interrupt request signal (inttpnov) is generated at the same time that the tpnovf bit is set to 1. the inttpnov signal is not generated in modes other than the free-running timer mode and the pulse width measurement mode. ? the tpnovf bit is not cleared to 0 even when the tpnovf bit or the tpnopt0 register are read when the tpnovf bit = 1. ? before clearing the tpnovf bit to 0 after the inttpnov signal has been generated, be sure to confirm (read) that the tpnovf bit is set to 1. ? the tpnovf bit can be both read and written, but the tpnovf bit cannot be set to 1 by software. writing 1 has no influence on the operation of tmpn. overflow occurred tpnovf bit 0 written or tpnctl0.tpnce bit = 0 7 <0> cautions 1. rewrite the tpnccs1 and tpnccs0 bits when the tpnce bit = 0. (the same value can be written when the tpnce bit = 1.) if re writing was mistakenly performed, clear the tpnce bit to 0 and then set the bits again. 2. be sure to clear bits 1 to 3, 6, and 7 to ?0?. chapter 7 16-bit timer/event counter p (tmp) user?s manual u16603ej5v1ud 251 (7) tmpn capture/compare register 0 (tpnccr0) the tpnccr0 register is a 16-bit re gister that can be used as a capture register or a compare register depending on the mode. this register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the tpnopt0.tpnccs0 bit. in the pulse width measurement mode, the tpnccr0 register can be used only as a capt ure register. in any other mode, this register can be used only as a compare register. the tpnccr0 register can be r ead or written during operation. this register can be read or written in 16-bit units. reset sets this register to 0000h. caution accessing the tpnccr0 register is prohibited in the following statuses. for details, see 3.4.9 (2) accessing specific on-chip peripheral i/o registers. ? when the cpu operates with the subclock a nd the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock tpnccr0 (n = 0 to 8) 12 10 8 6 4 2 after reset: 0000h r/w address: tp0ccr0 fffff596h, tp1ccr0 fffff5a6h, tp2ccr0 fffff5b6h, tp3ccr0 fffff5c6h, tp4ccr0 fffff5d6h, tp5ccr0 fffff5e6h, tp6ccr0 fffff5f6h, tp7ccr0 fffff606h, tp8ccr0 fffff616h 14 0 13 11 9 7 5 3 15 1 chapter 7 16-bit timer/event counter p (tmp) user?s manual u16603ej5v1ud 252 (a) function as compare register the tpnccr0 register can be rewritten even when the tpnctl0.tpnce bit = 1. the set value of the tpnccr0 register is transferred to the ccr0 buffer register. when the value of the 16-bit counter matches the value of the ccr0 buffer register, a compare match interrupt request signal (inttpncc0) is generated. if topn0 pin output is ena bled at this time, the output of the topn0 pin is inverted. when the tpnccr0 register is used as a cycle register in the interval timer mode, external event count mode, external trigger pulse output mode, one-shot pulse output mode, or pwm output mode, the value of the 16-bit counter is cleared (0000h) if its count va lue matches the value of the ccr0 buffer register. the compare register is not cleared when the tpnctl0.tpnce bit = 0. (b) function as capture register when the tpnccr0 register is used as a capture regi ster in the free-running timer mode, the count value of the 16-bit counter is stored in the tpnccr0 register if the valid ed ge of the capture trigger input pin (tipn0 pin) is detected. in the pulse-width measurement mode, the co unt value of the 16-bit counter is stored in the tpnccr0 register and the 16-bit counter is cleared (0000h) if the valid edge of the capture trigger input pin (tipn0) is detected. even if the capture operation and reading the tpn ccr0 register conflict, the correct value of the tpnccr0 register can be read. the capture register is cleared when the tpnctl0.tpnce bit = 0. remark n = 0 to 8 the following table shows the functions of the capture/compare re gister in each mode, and how to write data to the compare register. table 7-2. function of capture/co mpare register in each mode a nd how to write compare register operation mode capture/compare register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write note one-shot pulse output compare register anytime write pwm output compare register batch write note free-running timer capture/compare register anytime write pulse width measurement capture register none note triggered by writing to the tpnccr1 register remark for details of anytime write and batch write, see 7.6 (2) anytime write and batch write . chapter 7 16-bit timer/event counter p (tmp) user?s manual u16603ej5v1ud 253 (8) tmpn capture/compare register 1 (tpnccr1) the tpnccr1 register is a 16-bit re gister that can be used as a capture register or a compare register depending on the mode. this register can be used as a capture register or a compare register only in the free-running timer mode, depending on the setting of the tpnopt0.tpnccs1 bit. in the pulse width measurement mode, the tpnccr1 register can be used only as a capt ure register. in any other mode, this register can be used only as a compare register. the tpnccr1 register can be r ead or written during operation. this register can be read or written in 16-bit units. reset sets this register to 0000h. caution accessing the tpnccr1 register is prohibi ted in the following stat uses. for details, see 3.4.9 (2) accessing specific on-ch ip peripheral i/o registers. ? when the cpu operates with the subclock a nd the main clock oscillation is stopped ? when the cpu operates with th e internal oscillation clock tpnccr1 (n = 0 to 8) 12 10 8 6 4 2 after reset: 0000h r/w address: tp0ccr1 fffff598h, tp1ccr1 fffff5a8h, tp2ccr1 fffff5b8h, tp3ccr1 fffff5c8h, tp4ccr1 fffff5d8h, tp5ccr1 fffff5e8h, tp6ccr1 fffff5f8h, tp7ccr1 fffff608h, tp8ccr1 fffff618h 14 0 13 11 9 7 5 3 15 1 chapter 7 16-bit timer/event counter p (tmp) user?s manual u16603ej5v1ud 254 (a) function as compare register the tpnccr1 register can be rewritten even when the tpnctl0.tpnce bit = 1. the set value of the tpnccr1 register is transferred to the ccr1 buffer register. when the value of the 16-bit counter matches the value of the ccr1 buffer register, a compare match interrupt request signal (inttpncc1) is generated. if topn1 pin output is ena bled at this time, the output of the topn1 pin is inverted. the compare register is not cleared when the tpnctl0.tpnce bit = 0. (b) function as capture register when the tpnccr1 register is used as a capture regi ster in the free-running timer mode, the count value of the 16-bit counter is stored in the tpnccr1 register if the valid ed ge of the capture trigger input pin (tipn1 pin) is detected. in the pulse-width measurement mode, the co unt value of the 16-bit counter is stored in the tpnccr1 register and the 16-bit counter is cleared (0000h) if the valid edge of the capture trigger input pin (tipn1) is detected. even if the capture operation and reading the tpn ccr1 register conflict, the correct value of the tpnccr1 register can be read. the capture register is cleared when the tpnctl0.tpnce bit = 0. remark n = 0 to 8 the following table shows the functions of the capture/compare re gister in each mode, and how to write data to the compare register. table 7-3. function of capture/co mpare register in each mode a nd how to write compare register operation mode capture/compare register how to write compare register interval timer compare register anytime write external event counter compare register anytime write external trigger pulse output compare register batch write note one-shot pulse output compare register anytime write pwm output compare register batch write note free-running timer capture/compare register anytime write pulse width measurement capture register none note triggered by writing to the tpnccr1 register remark for anytime write and batch write, see 7.6 (2) anytime write and batch write . chapter 7 16-bit timer/event counter p (tmp) user?s manual u16603ej5v1ud 255 (9) tmpn counter read bu ffer register (tpncnt) the tpncnt register is a read buffer register that can read the count va lue of the 16-bit counter. if this register is read when the tpnctl0.tpnce bit = 1, the count value of the 16-bit timer can be read. this register is read-only, in 16-bit units. the value of the tpncnt register is cleared to 0000h when the tpnce bit = 0. if the tpncnt register is read at this time, the value of the 16-bit count er (ffffh) is not read, but 0000h is read. the value of the tpncnt register is cleared to 000 0h after reset, as the tpnce bit is cleared to 0. caution accessing the tpncnt regist er is prohibited in th e following statuses. for details, see 3.4.9 (2) accessing specific on-chip peripheral i/o registers. ? when the cpu operates with the subclock a nd the main clock oscillation is stopped ? when the cpu operates with the internal oscillation clock tpncnt (n = 0 to 8) 12 10 8 6 4 2 after reset: 0000h r address: tp0cnt fffff59ah, tp1cnt fffff5aah, tp2cnt fffff5bah, tp3cnt fffff5cah, tp4cnt fffff5dah, tp5cnt fffff5eah, tp6cnt fffff5fah, tp7cnt fffff60ah, tp8cnt fffff61ah 14 0 13 11 9 7 5 3 15 1 chapter 7 16-bit timer/event counter p (tmp) user?s manual u16603ej5v1ud 256 7.5 timer output operations the following table shows the operations and out put levels of the topn0 and topn1 pins. table 7-4. timer output control in each mode operation mode topn1 pin topn0 pin interval timer mode square wave output external event count mode none external trigger pulse output mode external trigger pulse output one-shot pulse output mode one-shot pulse output pwm output mode pwm output square wave output free-running timer mode square wave output (only when compare function is used) pulse width measurement mode none remark n = 0 to 8 table 7-5. truth table of topn0 and topn1 pins under control of timer output control bits tpnioc0.tpnolm bit tpnioc0.tpnoem bit tpnctl0.tpnce bit level of topnm pin 0 low-level output 0 low-level output 0 1 1 low level immediately before counting, high level after counting is started 0 high-level output 0 high-level output 1 1 1 high level immediately before counting, low level after counting is started remark n = 0 to 8 m = 0, 1 chapter 7 16-bit timer/event counter p (tmp) user?s manual u16603ej5v1ud 257 7.6 operation tmpn can perform the following operations. operation tpnctl1.tpnest bit (software trigger bit) tipn0 pin (external trigger input) capture/compare register setting compare register write interval timer mode invalid invalid compare only anytime write external event count mode note 1 invalid invalid compare only anytime write external trigger pulse output mode note 2 valid valid compare only batch write one-shot pulse output mode note 2 valid valid compare only anytime write pwm output mode invalid invalid compare only batch write free-running timer mode invalid invalid switching enabled anytime write pulse width measurement mode note 2 invalid invalid capture only not applicable notes 1. to use the external event count mode, specify that t he valid edge of the tipn0 pin capture trigger input is not detected (by clearing the tpnioc1.tpni s1 and tpnioc1.tpnis0 bits to ?00?). 2. to use the external trigger pulse output mode, one- shot pulse output mode, or pulse width measurement mode, select the internal clock (by setting the tpnctl1.tpneee bit to 0) as the count clock. remark n = 0 to 8 chapter 7 16-bit timer/event counter p (tmp) user?s manual u16603ej5v1ud 258 (1) counter basic operation this section explains the basic oper ation of the 16-bit counter. for details, refer to the description of the operation in each mode. remark n = 0 to 8 (a) counter start operation the 16-bit counter of tmpn starts countin g from the default value ffffh in all modes. it counts up from ffffh to 0000h, 0001h, 0002h, 0003h, and so on. (b) clear operation the 16-bit counter is cleared to 0000h when its value matches the value of the compare register and is cleared, and when its value is captured and cleared. the counting operation fr om ffffh to 0000h that takes place immediately after the counter has start ed counting or when the counter overflows is not a clearing operation. therefore, the inttpncc0 and inttpncc1 interrupt signals are not generated. (c) overflow operation the 16-bit counter overflows when the counter counts up from ffffh to 0000h in the free-running timer mode or pulse width measurement mode . if the counter overflows, the tpnopt0.tpnovf bit is set to 1 and an interrupt request signal (inttpnov) is generate d. note that the inttpnov signal is not generated under the following conditions. ? immediately after a counti ng operation has been started ? if the counter value matches the compare value ffffh and is cleared ? when ffffh is captured and cleared in the pulse width measurement mode and the counter counts up from ffffh to 0000h caution after the overflow interrupt request signa l (inttpnov) has been generated, be sure to check that the overflow flag (tpnovf bit) is set to 1. (d) counter read operation during counting operation the value of the 16-bit counter of tmpn can be re ad by using the tpncnt register during the count operation. when the tpnctl0.tpnce bit = 1, the val ue of the 16-bit counter can be read by reading the tpncnt register. when the tpnctl0.tpnce bit = 0, the 16-bit counter is ffffh and the tpncnt register is 0000h. (e) interrupt operation tmpn generates the following three types of interrupt request signals. ? inttpncc0 interrupt: this signal functions as a match interrupt request signal of the ccr0 buffer register and as a capture interrupt request signal to the tpnccr0 register. ? inttpncc1 interrupt: this signal functions as a match interrupt request signal of the ccr1 buffer register and as a capture interrupt request signal to the tpnccr1 register. ? inttpnov interrupt: this signal functions as an overflow interrupt request signal. chapter 7 16-bit timer/event counter p (tmp) user?s manual u16603ej5v1ud 259 (2) anytime write and batch write the tpnccr0 and tpnccr1 registers in tmpn can be re written during timer operation (tpnctl0.tpnce bit = 1), but the write method (anytime write, batch wr ite) of the ccr0 and ccr1 buffer registers differs depending on the mode. (a) anytime write in this mode, data is transferred at any time from the tpnccr0 and tpnccr1 registers to the ccr0 and ccr1 buffer registers during timer operation. (n = 0 to 8). figure 7-2. flowchart of basic operation for anytime write start initial settings ? set values to tpnccrm register ? timer operation enable (tpnce bit = 1) transfer values of tpnccrm register to ccrm buffer register timer operation ? match between 16-bit counter and ccr1 buffer register note ? match between 16-bit counter and ccr0 buffer register ? 16-bit counter clear & start inttpncc1 signal output tpnccrm register rewrite transfer to ccrm buffer register inttpncc0 signal output note the 16-bit counter is not cleared upon a match bet ween the 16-bit counter value and the ccr1 buffer register value. it is cleared upon a match between t he 16-bit counter value and the ccr0 buffer register value. remarks 1. the above flowchart illustrates an example of the operation in the interval timer mode. 2. n = 0 to 8 m = 0, 1 chapter 7 16-bit timer/event counter p (tmp) user?s manual u16603ej5v1ud 260 figure 7-3. timing of anytime write d 01 d 01 d 01 d 01 0000h tpnce bit = 1 d 02 d 02 d 11 d 11 d 11 d 12 d 12 d 12 d 02 d 11 0000h d 12 16-bit counter tpnccr0 register tpnccr1 register inttpncc0 signal inttpncc1 signal ccr0 buffer register ccr1 buffer register 0000h ffffh remarks 1. d 01 , d 02 : setting values of tpnccr0 register d 11 , d 12 : setting values of tpnccr1 register 2. the above timing chart illustrates an example of the operation in the interval timer mode. 3. n = 0 to 8 chapter 7 16-bit timer/event counter p (tmp) user?s manual u16603ej5v1ud 261 (b) batch write in this mode, data is transferred all at once from the tpnccr0 and tpnccr1 registers to the ccr0 and ccr1 buffer registers during timer operation. this data is transferred upon a match between the value of the ccr0 buffer register and the value of the 16-bit counter. transfer is enabled by writing to the tpnccr1 register. whether to enable or disable the next transfer timing is controlled by writing or not writing to the tpnccr1 register. in order for the setting value when the tpnccr0 and tpnccr1 registers are rewritten to become the 16- bit counter comparison value (in other words, in or der for this value to be transferred to the ccr0 and ccr1 buffer registers), it is necessary to rewrite the tpnccr0 register and then write to the tpnccr1 register before the 16-bit counter value and the ccr0 buff er register value match. therefore, the values of the tpnccr0 and tpnccr1 registers are transferr ed to the ccr0 and ccr1 buffer registers upon a match between the count value of the 16-bit counter and the value of the ccr0 buffer register. thus even when wishing only to rewrite the value of the tpnccr 0 register, also write the same value (same as preset value of the tpnccr1 regi ster) to the tpnccr1 register. chapter 7 16-bit timer/event counter p (tmp) user?s manual u16603ej5v1ud 262 figure 7-4. flowchart of basic operation for batch write start initial settings ? set values to tpnccrm register ? timer operation enable (tpnce bit = 1) transfer values of tpnccrm register to ccrm buffer register timer operation ? match between 16-bit counter and ccr1 buffer register note ? match between 16-bit counter and ccr0 buffer register ? 16-bit counter clear & start ? transfer of values of tpnccrm register to ccrm buffer register inttpncc1 signal output tpnccr0 register rewrite tpnccr1 register rewrite inttpncc0 signal output batch write enable note the 16-bit counter is not cleared upon a match bet ween the 16-bit counter value and the ccr1 buffer register value. it is cleared upon a match between t he 16-bit counter value and the ccr0 buffer register value. caution writing to the tpnccr1 regi ster includes enabling of batch wr ite. thus, rewrite the tpnccr1 register after rewriting the tpnccr0 register. remarks 1. the above flowchart illustrates an example of the operation in the pwm output mode. 2. n = 0 to 8 m = 0, 1 chapter 7 16-bit timer/event counter p (tmp) user?s manual u16603ej5v1ud 263 figure 7-5. timing of batch write d 01 d 01 d 02 d 03 0000h d 01 d 11 d 12 d 12 0000h d 11 tpnce bit = 1 note 1 d 02 d 02 d 03 d 11 d 12 d 12 d 12 d 12 16-bit counter tpnccr0 register tpnccr1 register inttpncc0 signal inttpncc1 signal topn1 pin output topn0 pin output ccr0 buffer register ccr1 buffer register note 1 note 1 note 1 same value write d 02 d 12 0000h d 03 d 12 note 2 note 3 ffffh notes 1. because the tpnccr1 register was not rewritten, d 03 is not transferred. 2. because the tpnccr1 register has been written (d 12 ), data is transferred to the ccr1 buffer register upon a match between the value of t he 16-bit counter and the value of the tpnccr0 register (d 01 ). 3. because the tpnccr1 register has been written (d 12 ), data is transferred to the ccr1 buffer register upon a match between the value of t he 16-bit counter and the value of the tpnccr0 register (d 02 ). remarks 1. d 01 , d 02 , d 03 : setting values of tpnccr0 register d 11 , d 12 : setting values of tpnccr1 register 2. the above timing chart illustrates the opera tion in the pwm output mode as an example. 3. n = 0 to 8 chapter 7 16-bit timer/event counter p (tmp) user?s manual u16603ej5v1ud 264 7.6.1 interval timer mode (t pnmd2 to tpnmd0 bits = 000) in the interval timer mode, an interrupt request signal (inttpncc0) is generated at the interval set by the tpnccr0 register if the tpnctl0.tpnce bit is set to 1. a square wave with a duty factor of 50% whose half cycle is equal to the interval can be output from the topn0 pin. the tpnccr1 register is not used in the interval timer m ode. however, the set value of the tpnccr1 register is transferred to the ccr1 buffer register, and when the count va lue of the 16-bit counter ma tches the value of the ccr1 buffer register, a compare match interrupt request signal (i nttpncc1) is generated. in addition, a square wave with a duty factor of 50%, which is inverted when the inttpncc1 signal is generated, can be ou tput from the topn1 pin. the value of the tpnccr0 and tpnccr1 registers c an be rewritten even while the timer is operating. figure 7-6. configuration of interval timer 16-bit counter output controller ccr0 buffer register tpnce bit tpnccr0 register count clock selection clear match signal topn0 pin inttpncc0 signal remark n = 0 to 8 figure 7-7. basic timing of operation in interval timer mode ffffh 16-bit counter 0000h tpnce bit tpnccr0 register topn0 pin output inttpncc0 signal d 0 d 0 d 0 d 0 d 0 interval (d 0 + 1) interval (d 0 + 1) interval (d 0 + 1) interval (d 0 + 1) remark n = 0 to 8 chapter 7 16-bit timer/event counter p (tmp) user?s manual u16603ej5v1ud 265 when the tpnce bit is set to 1, the va lue of the 16-bit counter is cleared fr om ffffh to 0000h in synchronization with the count clock, and t he counter starts counting. at this time, the out put of the topn0 pin is inverted. additionally, the set value of the tpnccr0 register is transferred to the ccr0 buffer register. when the count value of the 16-bit counter matches the valu e of the ccr0 buffer regi ster, the 16-bit counter is cleared to 0000h, the output of the topn0 pin is in verted, and a compare match interrupt request signal (inttpncc0) is generated. the interval can be calculated by the following expression. interval = (set value of tpnccr0 register + 1) count clock cycle remark n = 0 to 8 figure 7-8. register setting for in terval timer mode operation (1/3) (a) tmpn control register 0 (tpnctl0) 0/1 0 0 0 0 tpnctl0 select count clock 0: stop counting 1: enable counting 0/1 0/1 0/1 tpncks2 tpncks1 tpncks0 tpnce (b) tmpn control register 1 (tpnctl1) 0 0 0/1 note 00 tpnctl1 0, 0, 0: interval timer mode 0: operate on count clock selected by tpncks0 to tpncks2 bits 1: count with external event count input signal 000 tpnmd2 tpnmd1 tpnmd0 tpneee tpnest note the tpneee bit can be set to 1 only when the timer output (topn1) is used. however, set the tpnccr0 and tpnccr1 registers to the same value. chapter 7 16-bit timer/event counter p (tmp) user?s manual u16603ej5v1ud 266 figure 7-8. register setting for in terval timer mode operation (2/3) (c) tmpn i/o control register 0 (tpnioc0) 0 0 0 0 0/1 tpnioc0 0: disable topn0 pin output 1: enable topn0 pin output setting to output level of topn0 pin before count operation 0: low level 1: high level 0: disable topn1 pin output 1: enable topn1 pin output setting to output level of topn1 pin before count operation 0: low level 1: high level 0/1 0/1 0/1 tpnoe1 tpnol0 tpnoe0 tpnol1 (d) tmpn i/o control register 2 (tpnioc2) 0 0 0 0 0/1 note tpnioc2 select valid edge of external event count input (tipn0 pin). 0/1 note 00 tpnees0 tpnets1 tpnets0 tpnees1 note the tpnees1 and tpnees0 bits can be set only when the timer output (topn1) is used. however, set the tpnccr0 and tpnccr1 registers to the same value. (e) tmpn counter read bu ffer register (tpncnt) by reading the tpncnt register, the count va lue of the 16-bit counter can be read. (f) tmpn capture/compare register 0 (tpnccr0) if the tpnccr0 register is set to d 0 , the interval is as follows. interval = (d 0 + 1) count clock cycle remark n = 0 to 8 chapter 7 16-bit timer/event counter p (tmp) user?s manual u16603ej5v1ud 267 figure 7-8. register setting for in terval timer mode operation (3/3) (g) tmpn capture/compare register 1 (tpnccr1) the tpnccr1 register is not used in the interval timer mode. however, the set value of the tpnccr1 register is transferred to the ccr1 buffer register. when the count value of the 16-bit counter matches the value of the ccr1 buffer regi ster, the topn1 pin output is inverted and a compare match interrupt request signal (inttpncc1) is generated. by setting this register to the same value as the va lue set in the tpnccr0 register, a square wave with a duty factor of 50% can be output from the topn1 pin. when the tpnccr1 register is not used, it is recommended to set its value to ffffh. also mask the register by the interrupt mask flag (tpnccic1.tpnccmk1). remarks 1. tmpn i/o control register 1 (tpnioc1) and tmpn option register 0 (tpnopt0) are not used in the interval timer mode. 2. n = 0 to 8 chapter 7 16-bit timer/event counter p (tmp) user?s manual u16603ej5v1ud 268 (1) interval timer mode operation flow figure 7-9. software processing flow in interval timer mode tpnce bit = 1 tpnce bit = 0 register initial setting tpnctl0 register (tpncks0 to tpncks2 bits) tpnctl1 register, tpnioc0 register, tpnioc2 register note , tpnccr0 register initial setting of these registers is performed before setting the tpnce bit to 1. the tpncks0 to tpncks2 bits can be set at the same time when counting has been started (tpnce bit = 1). the counter is initialized and counting is stopped by clearing the tpnce bit to 0. the output level of the topn0 pin is as specified by the tpnioc0 register. start stop <1> count operation start flow <2> count operation stop flow d 0 <1> <2> d 0 d 0 d 0 ffffh 16-bit counter 0000h tpnce bit tpnccr0 register topn0 pin output inttpncc0 signal note the tpnees1 and tpnees0 bits can be set only when timer output (topn1) is used. however, set the tpnccr0 and tpnccr1 registers to the same value. remark n = 0 to 8 |